diff mbox series

[RESEND] Make Fujitsu Erratum 010001 patch can be applied on A64FX v1r0

Message ID 5FA513F682BE7F4EAAB8EE035D5B08E44E9363CC@G01JPEXMBKW02 (mailing list archive)
State New, archived
Headers show
Series [RESEND] Make Fujitsu Erratum 010001 patch can be applied on A64FX v1r0 | expand

Commit Message

Okamoto, Takayuki March 15, 2019, 12:22 p.m. UTC 
I resend the patch due to whitespace munging.

> -----Original Message-----
> From: James Morse <james.morse@arm.com>
> Sent: Wednesday, February 27, 2019 3:44 AM
> To: james.morse@arm.com; linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org; Catalin Marinas
> <catalin.marinas@arm.com>; Mark Rutland <mark.rutland@arm.com>; Will
> Deacon <will.deacon@arm.com>; Zhang, Lei <zhang.lei@jp.fujitsu.com>
> Subject: [PATCH v5] arm64: Add workaround for Fujitsu A64FX erratum
> 010001
> 
> +/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
> +#define MIDR_FUJITSU_ERRATUM_010001
> 	MIDR_FUJITSU_A64FX
> +#define MIDR_FUJITSU_ERRATUM_010001_MASK
> 	(~MIDR_VARIANT(1))

This workaround for the erratum should be applied for both A64FX v1r0 and
v0r0, however, the patch v5 is only enabled on A64FX v0r0(MIDR.Variant == 0
&& MIDR.Revision == 0).
This issue is caused by the macro MIDR_FUJITSU_ERRATUM_010001_MASK.

I have tested on both A64FX v1r0 and v0r0. This new patch will effect
only for A64FX.

--
Changed to be applied for not only A64FX v0r0 but also v1r0.

Signed-off-by: Zhang Lei <zhang.lei@jp.fujitsu.com>
---
 arch/arm64/include/asm/cputype.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Mark Rutland March 15, 2019, 3:12 p.m. UTC | #1 
On Fri, Mar 15, 2019 at 12:22:36PM +0000, Okamoto, Takayuki wrote:
> I resend the patch due to whitespace munging.
> 
> > -----Original Message-----
> > From: James Morse <james.morse@arm.com>
> > Sent: Wednesday, February 27, 2019 3:44 AM
> > To: james.morse@arm.com; linux-arm-kernel@lists.infradead.org
> > Cc: linux-kernel@vger.kernel.org; Catalin Marinas
> > <catalin.marinas@arm.com>; Mark Rutland <mark.rutland@arm.com>; Will
> > Deacon <will.deacon@arm.com>; Zhang, Lei <zhang.lei@jp.fujitsu.com>
> > Subject: [PATCH v5] arm64: Add workaround for Fujitsu A64FX erratum
> > 010001
> > 
> > +/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
> > +#define MIDR_FUJITSU_ERRATUM_010001
> > 	MIDR_FUJITSU_A64FX
> > +#define MIDR_FUJITSU_ERRATUM_010001_MASK
> > 	(~MIDR_VARIANT(1))
> 
> This workaround for the erratum should be applied for both A64FX v1r0 and
> v0r0, however, the patch v5 is only enabled on A64FX v0r0(MIDR.Variant == 0
> && MIDR.Revision == 0).
> This issue is caused by the macro MIDR_FUJITSU_ERRATUM_010001_MASK.
> 
> I have tested on both A64FX v1r0 and v0r0. This new patch will effect
> only for A64FX.
> 
> --
> Changed to be applied for not only A64FX v0r0 but also v1r0.
> 
> Signed-off-by: Zhang Lei <zhang.lei@jp.fujitsu.com>
> ---
>  arch/arm64/include/asm/cputype.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index 2afb133..1fb47b5 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -129,7 +129,7 @@
>  
>  /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
>  #define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX
> -#define MIDR_FUJITSU_ERRATUM_010001_MASK	(~MIDR_VARIANT(1))

The bug is is that MIDR_VARIANT() is meant to extract the variant from a
full MIDR value, not generate an in-place field value.

> +#define MIDR_FUJITSU_ERRATUM_010001_MASK	(~(0x1 << MIDR_VARIANT_SHIFT))

I beleive this can be:

#define MIDR_FUJITSU_ERRATUM_010001_MASK	(~MIDR_VAR_REV(1, 0))

But otherwise this looks fine to me.

Thanks,
Mark.

>  #define TCR_CLEAR_FUJITSU_ERRATUM_010001	(TCR_NFD1 | TCR_NFD0)
>  
>  #ifndef __ASSEMBLY__
> -- 
> 1.8.3.1
>
Zhang, Lei March 18, 2019, 3:05 a.m. UTC | #2 
Hi guys,

> -----Original Message-----
> From: linux-arm-kernel <linux-arm-kernel-bounces@lists.infradead.org> On
> Behalf Of Mark Rutland
> Sent: Saturday, March 16, 2019 12:13 AM
> To: Okamoto, Takayuki/岡本 高幸 <tokamoto@jp.fujitsu.com>
> Cc: 'Catalin Marinas' <catalin.marinas@arm.com>; 'Will Deacon'
> <will.deacon@arm.com>; 'linux-kernel@vger.kernel.org'
> <linux-kernel@vger.kernel.org>; Zhang, Lei/張 雷 <zhang.lei@jp.fujitsu.com>;
> 'James Morse' <james.morse@arm.com>; hange-folder>?
> <toggle-mailboxes@lakrids.cambridge.arm.com>;
> 'linux-arm-kernel@lists.infradead.org' <linux-arm-kernel@lists.infradead.org>
> Subject: Re: [RESEND PATCH] Make Fujitsu Erratum 010001 patch can be
> applied on A64FX v1r0
> 
> On Fri, Mar 15, 2019 at 12:22:36PM +0000, Okamoto, Takayuki wrote:
> > I resend the patch due to whitespace munging.
> >
> > > -----Original Message-----
> > > From: James Morse <james.morse@arm.com>
> > > Sent: Wednesday, February 27, 2019 3:44 AM
> > > To: james.morse@arm.com; linux-arm-kernel@lists.infradead.org
> > > Cc: linux-kernel@vger.kernel.org; Catalin Marinas
> > > <catalin.marinas@arm.com>; Mark Rutland <mark.rutland@arm.com>; Will
> > > Deacon <will.deacon@arm.com>; Zhang, Lei <zhang.lei@jp.fujitsu.com>
> > > Subject: [PATCH v5] arm64: Add workaround for Fujitsu A64FX erratum
> > > 010001
> > >
> > > +/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and
> > > +v1r0) */ #define MIDR_FUJITSU_ERRATUM_010001
> > > 	MIDR_FUJITSU_A64FX
> > > +#define MIDR_FUJITSU_ERRATUM_010001_MASK
> > > 	(~MIDR_VARIANT(1))
> >
> > This workaround for the erratum should be applied for both A64FX v1r0
> > and v0r0, however, the patch v5 is only enabled on A64FX
> > v0r0(MIDR.Variant == 0 && MIDR.Revision == 0).
> > This issue is caused by the macro MIDR_FUJITSU_ERRATUM_010001_MASK.
> >
> > I have tested on both A64FX v1r0 and v0r0. This new patch will effect
> > only for A64FX.
> >
> > --
> > Changed to be applied for not only A64FX v0r0 but also v1r0.
> >
> > Signed-off-by: Zhang Lei <zhang.lei@jp.fujitsu.com>
> > ---
> >  arch/arm64/include/asm/cputype.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/include/asm/cputype.h
> > b/arch/arm64/include/asm/cputype.h
> > index 2afb133..1fb47b5 100644
> > --- a/arch/arm64/include/asm/cputype.h
> > +++ b/arch/arm64/include/asm/cputype.h
> > @@ -129,7 +129,7 @@
> >
> >  /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
> >  #define MIDR_FUJITSU_ERRATUM_010001
> 	MIDR_FUJITSU_A64FX
> > -#define MIDR_FUJITSU_ERRATUM_010001_MASK
> 	(~MIDR_VARIANT(1))
> 
> The bug is is that MIDR_VARIANT() is meant to extract the variant from a full
> MIDR value, not generate an in-place field value.
> 
> > +#define MIDR_FUJITSU_ERRATUM_010001_MASK	(~(0x1 <<
> MIDR_VARIANT_SHIFT))
> 
> I beleive this can be:
> 
> #define MIDR_FUJITSU_ERRATUM_010001_MASK	(~MIDR_VAR_REV(1,
> 0))

Thanks for your comments.
I also have considered to use MIDR_CPU_VAR_REV macro,
but the implication of (~MIDR_CPU_VAR_REV(1, 0)) is "NOT v1r0".
I think it may cause confusion, so I choose the
simple way (~(0x1 << MIDR_VARIANT_SHIFT)).

> But otherwise this looks fine to me.

Will this patch be merged to v5.1?

Thanks,
Zhang Lei
Mark Rutland March 18, 2019, 12:06 p.m. UTC | #3 
On Mon, Mar 18, 2019 at 03:05:09AM +0000, Zhang, Lei wrote:
> Thanks for your comments.
> I also have considered to use MIDR_CPU_VAR_REV macro,
> but the implication of (~MIDR_CPU_VAR_REV(1, 0)) is "NOT v1r0".
> I think it may cause confusion, so I choose the
> simple way (~(0x1 << MIDR_VARIANT_SHIFT)).

I think that either way is just as confusing, and the fact we're
assigning it to a mask (of bits to preserve) should make this clear. For
consistency, I'd prefer to use MIDR_CPU_VAR_REV().

Catalin, are you happy to take the below as a fix for v5.1?

Thanks,
Mark.

---->8----
From 6439e9c0b1525e9d4c7be65552e6f2b1f9d1dbe0 Mon Sep 17 00:00:00 2001
From: "Okamoto, Takayuki" <tokamoto@jp.fujitsu.com>
Date: Fri, 15 Mar 2019 12:22:36 +0000
Subject: [PATCH] arm64: apply workaround on A64FX v1r0

Fujitsu erratum 010001 applies to A64FX v0r0 and v1r0, and we try to
handle either by masking MIDR with MIDR_FUJITSU_ERRATUM_010001_MASK
before comparing it to MIDR_FUJITSU_ERRATUM_010001.

Unfortunately, MIDR_FUJITSU_ERRATUM_010001 is constructed incorrectly
using MIDR_VARIANT(), which is intended to extract the variant field
from MIDR_EL1, rather than generate the field in-place. This results in
MIDR_FUJITSU_ERRATUM_010001 being all-ones, and we only match A64FX
v0r0.

This patch uses MIDR_CPU_VAR_REV() to generate an in-place mask for the
variant field, ensuring the we match both v0r0 and v1r0.

Fixes: 3e32131abc311a5c ("arm64: Add workaround for Fujitsu A64FX erratum 010001")
Signed-off-by: Zhang Lei <zhang.lei@jp.fujitsu.com>
[Mark: use MIDR_CPU_VAR_REV(), reword commit message]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
 arch/arm64/include/asm/cputype.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 2afb1338b48a..f3b659587a36 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -129,7 +129,7 @@
 
 /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
 #define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX
-#define MIDR_FUJITSU_ERRATUM_010001_MASK	(~MIDR_VARIANT(1))
+#define MIDR_FUJITSU_ERRATUM_010001_MASK	(~MIDR_CPU_VAR_REV(1, 0))
 #define TCR_CLEAR_FUJITSU_ERRATUM_010001	(TCR_NFD1 | TCR_NFD0)
 
 #ifndef __ASSEMBLY__
Catalin Marinas March 19, 2019, 12:52 p.m. UTC | #4 
On Mon, Mar 18, 2019 at 12:06:06PM +0000, Mark Rutland wrote:
> From 6439e9c0b1525e9d4c7be65552e6f2b1f9d1dbe0 Mon Sep 17 00:00:00 2001
> From: "Okamoto, Takayuki" <tokamoto@jp.fujitsu.com>
> Date: Fri, 15 Mar 2019 12:22:36 +0000
> Subject: [PATCH] arm64: apply workaround on A64FX v1r0
> 
> Fujitsu erratum 010001 applies to A64FX v0r0 and v1r0, and we try to
> handle either by masking MIDR with MIDR_FUJITSU_ERRATUM_010001_MASK
> before comparing it to MIDR_FUJITSU_ERRATUM_010001.
> 
> Unfortunately, MIDR_FUJITSU_ERRATUM_010001 is constructed incorrectly
> using MIDR_VARIANT(), which is intended to extract the variant field
> from MIDR_EL1, rather than generate the field in-place. This results in
> MIDR_FUJITSU_ERRATUM_010001 being all-ones, and we only match A64FX
> v0r0.
> 
> This patch uses MIDR_CPU_VAR_REV() to generate an in-place mask for the
> variant field, ensuring the we match both v0r0 and v1r0.
> 
> Fixes: 3e32131abc311a5c ("arm64: Add workaround for Fujitsu A64FX erratum 010001")
> Signed-off-by: Zhang Lei <zhang.lei@jp.fujitsu.com>
> [Mark: use MIDR_CPU_VAR_REV(), reword commit message]
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>

Thanks. Mark's variant queued for 5.1-rc2.
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 2afb133..1fb47b5 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -129,7 +129,7 @@ 
 
 /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
 #define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX
-#define MIDR_FUJITSU_ERRATUM_010001_MASK	(~MIDR_VARIANT(1))
+#define MIDR_FUJITSU_ERRATUM_010001_MASK	(~(0x1 << MIDR_VARIANT_SHIFT))
 #define TCR_CLEAR_FUJITSU_ERRATUM_010001	(TCR_NFD1 | TCR_NFD0)
 
 #ifndef __ASSEMBLY__