diff mbox series

x86/msr: Shorten ARCH_CAPABILITIES_* constants

Message ID 1552909548-22278-1-git-send-email-andrew.cooper3@citrix.com (mailing list archive)
State New, archived
Headers show
Series x86/msr: Shorten ARCH_CAPABILITIES_* constants | expand

Commit Message

Andrew Cooper March 18, 2019, 11:45 a.m. UTC 
They are unnecesserily verbose, and ARCH_CAPS_* is already the more common
version.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
CC: Wei Liu <wei.liu2@citrix.com>
CC: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/spec_ctrl.c        | 10 +++++-----
 xen/include/asm-x86/msr-index.h |  4 ++--
 2 files changed, 7 insertions(+), 7 deletions(-)

Comments

Jan Beulich March 18, 2019, 12:28 p.m. UTC | #1 
>>> On 18.03.19 at 12:45, <andrew.cooper3@citrix.com> wrote:
> They are unnecesserily verbose, and ARCH_CAPS_* is already the more common
> version.
> 
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>

Acked-by: Jan Beulich <jbeulich@suse.com>
diff mbox series

Patch

diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index ad72ecd..22bfc5a 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -230,8 +230,8 @@  static void __init print_details(enum ind_thunk thunk, uint64_t caps)
            (_7d0 & cpufeat_mask(X86_FEATURE_L1D_FLUSH)) ? " L1D_FLUSH" : "",
            (_7d0 & cpufeat_mask(X86_FEATURE_SSBD))  ? " SSBD"      : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB))  ? " IBPB"      : "",
-           (caps & ARCH_CAPABILITIES_IBRS_ALL)      ? " IBRS_ALL"  : "",
-           (caps & ARCH_CAPABILITIES_RDCL_NO)       ? " RDCL_NO"   : "",
+           (caps & ARCH_CAPS_IBRS_ALL)              ? " IBRS_ALL"  : "",
+           (caps & ARCH_CAPS_RDCL_NO)               ? " RDCL_NO"   : "",
            (caps & ARCH_CAPS_RSBA)                  ? " RSBA"      : "",
            (caps & ARCH_CAPS_SKIP_L1DFL)            ? " SKIP_L1DFL": "",
            (caps & ARCH_CAPS_SSB_NO)                ? " SSB_NO"    : "");
@@ -549,7 +549,7 @@  static __init void l1tf_calculations(uint64_t caps)
     }
 
     /* Any processor advertising RDCL_NO should be not vulnerable to L1TF. */
-    if ( caps & ARCH_CAPABILITIES_RDCL_NO )
+    if ( caps & ARCH_CAPS_RDCL_NO )
         cpu_has_bug_l1tf = false;
 
     if ( cpu_has_bug_l1tf && hit_default )
@@ -613,9 +613,9 @@  int8_t __read_mostly opt_xpti_domu = -1;
 static __init void xpti_init_default(uint64_t caps)
 {
     if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
-        caps = ARCH_CAPABILITIES_RDCL_NO;
+        caps = ARCH_CAPS_RDCL_NO;
 
-    if ( caps & ARCH_CAPABILITIES_RDCL_NO )
+    if ( caps & ARCH_CAPS_RDCL_NO )
     {
         if ( opt_xpti_hwdom < 0 )
             opt_xpti_hwdom = 0;
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index c6e1d87..11512d4 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -42,8 +42,8 @@ 
 #define PRED_CMD_IBPB			(_AC(1, ULL) << 0)
 
 #define MSR_ARCH_CAPABILITIES		0x0000010a
-#define ARCH_CAPABILITIES_RDCL_NO	(_AC(1, ULL) << 0)
-#define ARCH_CAPABILITIES_IBRS_ALL	(_AC(1, ULL) << 1)
+#define ARCH_CAPS_RDCL_NO		(_AC(1, ULL) << 0)
+#define ARCH_CAPS_IBRS_ALL		(_AC(1, ULL) << 1)
 #define ARCH_CAPS_RSBA			(_AC(1, ULL) << 2)
 #define ARCH_CAPS_SKIP_L1DFL		(_AC(1, ULL) << 3)
 #define ARCH_CAPS_SSB_NO		(_AC(1, ULL) << 4)