| Message ID | 20190318161317.30918-8-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Clean up intel_color_check() | expand |
On Mon, Mar 18, 2019 at 06:13:14PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Provide a separate .color_check() for BDW+ where we currently > provide the split gamma mode etc. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Patches #5-7: Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/intel_color.c | 39 ++++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c > index e2a1c823650b..6507e5f79c06 100644 > --- a/drivers/gpu/drm/i915/intel_color.c > +++ b/drivers/gpu/drm/i915/intel_color.c > @@ -871,6 +871,43 @@ static int chv_color_check(struct intel_crtc_state *crtc_state) > return 0; > } > > +static u32 bdw_gamma_mode(const struct intel_crtc_state *crtc_state) > +{ > + if (!crtc_state->gamma_enable || > + crtc_state_is_legacy_gamma(crtc_state)) > + return GAMMA_MODE_MODE_8BIT; > + else > + return GAMMA_MODE_MODE_SPLIT; > +} > + > +static int bdw_color_check(struct intel_crtc_state *crtc_state) > +{ > + int ret; > + > + ret = check_luts(crtc_state); > + if (ret) > + return ret; > + > + crtc_state->gamma_enable = > + (crtc_state->base.gamma_lut || > + crtc_state->base.degamma_lut) && > + !crtc_state->c8_planes; > + > + crtc_state->csc_enable = > + crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || > + crtc_state->base.ctm || crtc_state->limited_color_range; > + > + crtc_state->gamma_mode = bdw_gamma_mode(crtc_state); > + > + crtc_state->csc_mode = 0; > + > + ret = intel_color_add_affected_planes(crtc_state); > + if (ret) > + return ret; > + > + return 0; > +} > + > static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state) > { > if (!crtc_state->gamma_enable || > @@ -1037,6 +1074,8 @@ void intel_color_init(struct intel_crtc *crtc) > dev_priv->display.color_check = icl_color_check; > else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > dev_priv->display.color_check = glk_color_check; > + else if (INTEL_GEN(dev_priv) >= 8) > + dev_priv->display.color_check = bdw_color_check; > else > dev_priv->display.color_check = _intel_color_check; > } > -- > 2.19.2 >
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index e2a1c823650b..6507e5f79c06 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -871,6 +871,43 @@ static int chv_color_check(struct intel_crtc_state *crtc_state) return 0; } +static u32 bdw_gamma_mode(const struct intel_crtc_state *crtc_state) +{ + if (!crtc_state->gamma_enable || + crtc_state_is_legacy_gamma(crtc_state)) + return GAMMA_MODE_MODE_8BIT; + else + return GAMMA_MODE_MODE_SPLIT; +} + +static int bdw_color_check(struct intel_crtc_state *crtc_state) +{ + int ret; + + ret = check_luts(crtc_state); + if (ret) + return ret; + + crtc_state->gamma_enable = + (crtc_state->base.gamma_lut || + crtc_state->base.degamma_lut) && + !crtc_state->c8_planes; + + crtc_state->csc_enable = + crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || + crtc_state->base.ctm || crtc_state->limited_color_range; + + crtc_state->gamma_mode = bdw_gamma_mode(crtc_state); + + crtc_state->csc_mode = 0; + + ret = intel_color_add_affected_planes(crtc_state); + if (ret) + return ret; + + return 0; +} + static u32 glk_gamma_mode(const struct intel_crtc_state *crtc_state) { if (!crtc_state->gamma_enable || @@ -1037,6 +1074,8 @@ void intel_color_init(struct intel_crtc *crtc) dev_priv->display.color_check = icl_color_check; else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) dev_priv->display.color_check = glk_color_check; + else if (INTEL_GEN(dev_priv) >= 8) + dev_priv->display.color_check = bdw_color_check; else dev_priv->display.color_check = _intel_color_check; }