[1/9] arm64: dts: renesas: r8a774c0: Add secondary CA53 CPU core
diff mbox series

Message ID 1553246370-60751-2-git-send-email-biju.das@bp.renesas.com
State Accepted
Delegated to: Nobuhiro Iwamatsu
Headers show
Series
  • Add SMP/INTC-EX/PFC/GPIO support
Related show

Commit Message

Biju Das March 22, 2019, 9:19 a.m. UTC
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Add a device node for the second Cortex-A53 CPU core on the Renesas
RZ/G2E (a.k.a r8a774c0) SoC, and adjust the interrupt delivery masks
for the ARM Generic Interrupt Controller and Architectured Timer.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 9b55a05ebfbe41bfb4c2aa98a81a46f2031e599f)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

Comments

Nobuhiro Iwamatsu April 10, 2019, 11:14 p.m. UTC | #1
Hi, Diju.

> -----Original Message-----
> From: cip-dev-bounces@lists.cip-project.org
> [mailto:cip-dev-bounces@lists.cip-project.org] On Behalf Of Biju Das
> Sent: Friday, March 22, 2019 6:19 PM
> To: cip-dev@lists.cip-project.org
> Cc: Biju Das <biju.das@bp.renesas.com>
> Subject: [cip-dev] [PATCH 1/9] arm64: dts: renesas: r8a774c0: Add
> secondary CA53 CPU core
> 
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> 
> Add a device node for the second Cortex-A53 CPU core on the Renesas RZ/G2E
> (a.k.a r8a774c0) SoC, and adjust the interrupt delivery masks for the
> ARM Generic Interrupt Controller and Architectured Timer.

I think that 'Architected Timer' is correct, not 'Architectured Timer'.
If my point is correct, I will fix and apply the commit message.

Other patches are looks good to me.

Best regards,
  Nobuhiro
Biju Das April 11, 2019, 6:54 a.m. UTC | #2
Hi Nobuhiro-San,

Thanks for the feedback.

Regards,
Biju

> -----Original Message-----
> From: nobuhiro1.iwamatsu@toshiba.co.jp
> <nobuhiro1.iwamatsu@toshiba.co.jp>
> Sent: 11 April 2019 00:14
> To: Biju Das <biju.das@bp.renesas.com>; cip-dev@lists.cip-project.org
> Subject: RE: [cip-dev] [PATCH 1/9] arm64: dts: renesas: r8a774c0: Add
> secondary CA53 CPU core
> 
> Hi, Diju.
> 
> > -----Original Message-----
> > From: cip-dev-bounces@lists.cip-project.org
> > [mailto:cip-dev-bounces@lists.cip-project.org] On Behalf Of Biju Das
> > Sent: Friday, March 22, 2019 6:19 PM
> > To: cip-dev@lists.cip-project.org
> > Cc: Biju Das <biju.das@bp.renesas.com>
> > Subject: [cip-dev] [PATCH 1/9] arm64: dts: renesas: r8a774c0: Add
> > secondary CA53 CPU core
> >
> > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > Add a device node for the second Cortex-A53 CPU core on the Renesas
> > RZ/G2E (a.k.a r8a774c0) SoC, and adjust the interrupt delivery masks
> > for the ARM Generic Interrupt Controller and Architectured Timer.
> 
> I think that 'Architected Timer' is correct, not 'Architectured Timer'.
> If my point is correct, I will fix and apply the commit message.
> 
> Other patches are looks good to me.

I believe it is correct. see the link below.

https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/arch_timer.txt

Already the cherry-picked patch from upstream is reviewed by wider people.
So I believe it is not good to change the commit messages or ordering of patches.

We have upstreamed RZ/G2[ME] patches in specific order. So we expect the same order in cip kernel as well.
Like SoC definitions,SYSC,RST,CLK,Pinctrl , SoC DTSI,Board DTSI and the rest of the drivers.

We may be wrong. So please correct us if we are wrong.

Regards,
Biju
Biju Das April 11, 2019, 6:59 a.m. UTC | #3
Hi Nobuhiro-San,

> -----Original Message-----
> From: Biju Das
> Sent: 11 April 2019 07:55
> To: nobuhiro1.iwamatsu@toshiba.co.jp; cip-dev@lists.cip-project.org
> Cc: Chris Paterson <Chris.Paterson2@renesas.com>; Fabrizio Castro
> <fabrizio.castro@bp.renesas.com>
> Subject: RE: [cip-dev] [PATCH 1/9] arm64: dts: renesas: r8a774c0: Add
> secondary CA53 CPU core
> 
> 
> Hi Nobuhiro-San,
> 
> Thanks for the feedback.
> 
> Regards,
> Biju
> 
> > -----Original Message-----
> > From: nobuhiro1.iwamatsu@toshiba.co.jp
> > <nobuhiro1.iwamatsu@toshiba.co.jp>
> > Sent: 11 April 2019 00:14
> > To: Biju Das <biju.das@bp.renesas.com>; cip-dev@lists.cip-project.org
> > Subject: RE: [cip-dev] [PATCH 1/9] arm64: dts: renesas: r8a774c0: Add
> > secondary CA53 CPU core
> >
> > Hi, Diju.
> >
> > > -----Original Message-----
> > > From: cip-dev-bounces@lists.cip-project.org
> > > [mailto:cip-dev-bounces@lists.cip-project.org] On Behalf Of Biju Das
> > > Sent: Friday, March 22, 2019 6:19 PM
> > > To: cip-dev@lists.cip-project.org
> > > Cc: Biju Das <biju.das@bp.renesas.com>
> > > Subject: [cip-dev] [PATCH 1/9] arm64: dts: renesas: r8a774c0: Add
> > > secondary CA53 CPU core
> > >
> > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >
> > > Add a device node for the second Cortex-A53 CPU core on the Renesas
> > > RZ/G2E (a.k.a r8a774c0) SoC, and adjust the interrupt delivery masks
> > > for the ARM Generic Interrupt Controller and Architectured Timer.
> >
> > I think that 'Architected Timer' is correct, not 'Architectured Timer'.

Yes, you are correct, as per the below link. 

https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/arch _timer.txt

> > If my point is correct, I will fix and apply the commit message.
> > Other patches are looks good to me.

> I believe it is correct. see the link below.
> 
> https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/arch
> _timer.txt
> 
> Already the cherry-picked patch from upstream is reviewed by wider people.
> So I believe it is not good to change the commit messages or ordering of
> patches.
> 
> We have upstreamed RZ/G2[ME] patches in specific order. So we expect the
> same order in cip kernel as well.
> Like SoC definitions,SYSC,RST,CLK,Pinctrl , SoC DTSI,Board DTSI and the rest
> of the drivers.
> 
> We may be wrong. So please correct us if we are wrong.
> 
> Regards,
> Biju
>
Nobuhiro Iwamatsu April 11, 2019, 9:34 a.m. UTC | #4
Hi, Biju.

2019年4月11日(木) 15:55 Biju Das <biju.das@bp.renesas.com>:
>
>
> Hi Nobuhiro-San,
>
> Thanks for the feedback.
>
> Regards,
> Biju
>
> > -----Original Message-----
> > From: nobuhiro1.iwamatsu@toshiba.co.jp
> > <nobuhiro1.iwamatsu@toshiba.co.jp>
> > Sent: 11 April 2019 00:14
> > To: Biju Das <biju.das@bp.renesas.com>; cip-dev@lists.cip-project.org
> > Subject: RE: [cip-dev] [PATCH 1/9] arm64: dts: renesas: r8a774c0: Add
> > secondary CA53 CPU core
> >
> > Hi, Diju.
> >
> > > -----Original Message-----
> > > From: cip-dev-bounces@lists.cip-project.org
> > > [mailto:cip-dev-bounces@lists.cip-project.org] On Behalf Of Biju Das
> > > Sent: Friday, March 22, 2019 6:19 PM
> > > To: cip-dev@lists.cip-project.org
> > > Cc: Biju Das <biju.das@bp.renesas.com>
> > > Subject: [cip-dev] [PATCH 1/9] arm64: dts: renesas: r8a774c0: Add
> > > secondary CA53 CPU core
> > >
> > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >
> > > Add a device node for the second Cortex-A53 CPU core on the Renesas
> > > RZ/G2E (a.k.a r8a774c0) SoC, and adjust the interrupt delivery masks
> > > for the ARM Generic Interrupt Controller and Architectured Timer.
> >
> > I think that 'Architected Timer' is correct, not 'Architectured Timer'.
> > If my point is correct, I will fix and apply the commit message.
> >
> > Other patches are looks good to me.
>
> I believe it is correct. see the link below.
>
> https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/arch_timer.txt
>
> Already the cherry-picked patch from upstream is reviewed by wider people.
> So I believe it is not good to change the commit messages or ordering of patches.
>
> We have upstreamed RZ/G2[ME] patches in specific order. So we expect the same order in cip kernel as well.
> Like SoC definitions,SYSC,RST,CLK,Pinctrl , SoC DTSI,Board DTSI and the rest of the drivers.
>
> We may be wrong. So please correct us if we are wrong.

I do not intend to change the patch application order.
However, since our CIP kernel needs to be maintained on a long-term,
I think it is better to fix the problems that we noticed and include the
corrected content in the commit message.

>
> Regards,
> Biju

Best regards,
  Nobuhiro

Patch
diff mbox series

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 872efa7..5bea23e 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -48,7 +48,6 @@ 
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		/* 1 core only at this point */
 		a53_0: cpu@0 {
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0>;
@@ -58,6 +57,15 @@ 
 			enable-method = "psci";
 		};
 
+		a53_1: cpu@1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <1>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+		};
+
 		L2_CA53: cache-controller-0 {
 			compatible = "cache";
 			power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
@@ -82,8 +90,9 @@ 
 
 	pmu_a53 {
 		compatible = "arm,cortex-a53-pmu";
-		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&a53_0>;
+		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&a53_0>, <&a53_1>;
 	};
 
 	psci {
@@ -423,7 +432,7 @@ 
 			      <0x0 0xf1040000 0 0x20000>,
 			      <0x0 0xf1060000 0 0x20000>;
 			interrupts = <GIC_PPI 9
-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 			clocks = <&cpg CPG_MOD 408>;
 			clock-names = "clk";
 			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
@@ -438,10 +447,10 @@ 
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
 	/* External USB clocks - can be overridden by the board */