diff mbox series

[for-4.0,3/3] target/ppc: Consolidate 64-bit server processor detection in a helper

Message ID 155327783157.1283071.3747129891004927299.stgit@bahia.lan (mailing list archive)
State New, archived
Headers show
Series target/ppc: Fix pseries.cap-ibs=workaround with TCG | expand

Commit Message

Greg Kurz March 22, 2019, 6:03 p.m. UTC 
We use PPC_SEGMENT_64B in various places to guard code that is specific
to 64-bit server processors compliant with arch 2.x. Consolidate the
logic in a helper macro with an explicit name.

Signed-off-by: Greg Kurz <groug@kaod.org>
---
 hw/ppc/ppc.c             |    2 +-
 target/ppc/cpu.h         |    6 ++++++
 target/ppc/helper_regs.h |    2 +-
 target/ppc/translate.c   |   10 ++++------
 4 files changed, 12 insertions(+), 8 deletions(-)

Comments

Suraj Jitindar Singh March 25, 2019, 12:38 a.m. UTC | #1 
On Fri, 2019-03-22 at 19:03 +0100, Greg Kurz wrote:
> We use PPC_SEGMENT_64B in various places to guard code that is
> specific
> to 64-bit server processors compliant with arch 2.x. Consolidate the
> logic in a helper macro with an explicit name.

Tested-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>

> 
> Signed-off-by: Greg Kurz <groug@kaod.org>
> ---
>  hw/ppc/ppc.c             |    2 +-
>  target/ppc/cpu.h         |    6 ++++++
>  target/ppc/helper_regs.h |    2 +-
>  target/ppc/translate.c   |   10 ++++------
>  4 files changed, 12 insertions(+), 8 deletions(-)
> 
> diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
> index 49d57469fb34..ad20584f268d 100644
> --- a/hw/ppc/ppc.c
> +++ b/hw/ppc/ppc.c
> @@ -1101,7 +1101,7 @@ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env,
> uint32_t freq)
>      tb_env = g_malloc0(sizeof(ppc_tb_t));
>      env->tb_env = tb_env;
>      tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
> -    if (env->insns_flags & PPC_SEGMENT_64B) {
> +    if (is_book3s_arch2x(env)) {
>          /* All Book3S 64bit CPUs implement level based DEC logic */
>          tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;
>      }
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index fc12b4688e8c..070717758452 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -2409,6 +2409,12 @@ enum {
>  target_ulong cpu_read_xer(CPUPPCState *env);
>  void cpu_write_xer(CPUPPCState *env, target_ulong xer);
>  
> +/*
> + * All 64-bit server processors compliant with arch 2.x, ie. 970 and
> newer,
> + * have PPC_SEGMENT_64B.
> + */
> +#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags &
> PPC_SEGMENT_64B))
> +
>  static inline void cpu_get_tb_cpu_state(CPUPPCState *env,
> target_ulong *pc,
>                                          target_ulong *cs_base,
> uint32_t *flags)
>  {
> diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h
> index a2205e1044c9..c863abc0bfc3 100644
> --- a/target/ppc/helper_regs.h
> +++ b/target/ppc/helper_regs.h
> @@ -152,7 +152,7 @@ static inline int hreg_store_msr(CPUPPCState
> *env, target_ulong value,
>       * - 64-bit embedded implementations do not need any operation
> to be
>       *   performed when PR is set.
>       */
> -    if ((env->insns_flags & PPC_SEGMENT_64B) && ((value >> MSR_PR) &
> 1)) {
> +    if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) {
>          value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
>      }
>  #endif
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index d3aaa6482c6a..576210d901ad 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -3755,7 +3755,7 @@ static void gen_bcond(DisasContext *ctx, int
> type)
>               * arch 2.x, do implement a "test and decrement" logic
> instead,
>               * as described in their respective UMs.
>               */
> -            if (unlikely(!(ctx->insns_flags & PPC_SEGMENT_64B))) {
> +            if (unlikely(!is_book3s_arch2x(ctx))) {
>                  gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
>                  tcg_temp_free(temp);
>                  tcg_temp_free(target);
> @@ -3913,7 +3913,7 @@ static void gen_rfi(DisasContext *ctx)
>      /* This instruction doesn't exist anymore on 64-bit server
>       * processors compliant with arch 2.x
>       */
> -    if (ctx->insns_flags & PPC_SEGMENT_64B) {
> +    if (is_book3s_arch2x(ctx)) {
>          gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
>          return;
>      }
> @@ -6535,8 +6535,7 @@ static void gen_msgclr(DisasContext *ctx)
>      GEN_PRIV;
>  #else
>      CHK_HV;
> -    /* 64-bit server processors compliant with arch 2.x */
> -    if (ctx->insns_flags & PPC_SEGMENT_64B) {
> +    if (is_book3s_arch2x(ctx)) {
>          gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
>      } else {
>          gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
> @@ -6550,8 +6549,7 @@ static void gen_msgsnd(DisasContext *ctx)
>      GEN_PRIV;
>  #else
>      CHK_HV;
> -    /* 64-bit server processors compliant with arch 2.x */
> -    if (ctx->insns_flags & PPC_SEGMENT_64B) {
> +    if (is_book3s_arch2x(ctx)) {
>          gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
>      } else {
>          gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
> 
>
David Gibson March 25, 2019, 6:40 a.m. UTC | #2 
On Fri, Mar 22, 2019 at 07:03:51PM +0100, Greg Kurz wrote:
> We use PPC_SEGMENT_64B in various places to guard code that is specific
> to 64-bit server processors compliant with arch 2.x. Consolidate the
> logic in a helper macro with an explicit name.
> 
> Signed-off-by: Greg Kurz <groug@kaod.org>

This mitigates my concern about re-using the PPC_SEGMENT_64B bit
discussed in reply to the previous patch, since it leaves only one
place to fix instead of a bunch.

> ---
>  hw/ppc/ppc.c             |    2 +-
>  target/ppc/cpu.h         |    6 ++++++
>  target/ppc/helper_regs.h |    2 +-
>  target/ppc/translate.c   |   10 ++++------
>  4 files changed, 12 insertions(+), 8 deletions(-)
> 
> diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
> index 49d57469fb34..ad20584f268d 100644
> --- a/hw/ppc/ppc.c
> +++ b/hw/ppc/ppc.c
> @@ -1101,7 +1101,7 @@ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
>      tb_env = g_malloc0(sizeof(ppc_tb_t));
>      env->tb_env = tb_env;
>      tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
> -    if (env->insns_flags & PPC_SEGMENT_64B) {
> +    if (is_book3s_arch2x(env)) {
>          /* All Book3S 64bit CPUs implement level based DEC logic */
>          tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;
>      }
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index fc12b4688e8c..070717758452 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -2409,6 +2409,12 @@ enum {
>  target_ulong cpu_read_xer(CPUPPCState *env);
>  void cpu_write_xer(CPUPPCState *env, target_ulong xer);
>  
> +/*
> + * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
> + * have PPC_SEGMENT_64B.
> + */
> +#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
> +
>  static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
>                                          target_ulong *cs_base, uint32_t *flags)
>  {
> diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h
> index a2205e1044c9..c863abc0bfc3 100644
> --- a/target/ppc/helper_regs.h
> +++ b/target/ppc/helper_regs.h
> @@ -152,7 +152,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
>       * - 64-bit embedded implementations do not need any operation to be
>       *   performed when PR is set.
>       */
> -    if ((env->insns_flags & PPC_SEGMENT_64B) && ((value >> MSR_PR) & 1)) {
> +    if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) {
>          value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
>      }
>  #endif
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index d3aaa6482c6a..576210d901ad 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -3755,7 +3755,7 @@ static void gen_bcond(DisasContext *ctx, int type)
>               * arch 2.x, do implement a "test and decrement" logic instead,
>               * as described in their respective UMs.
>               */
> -            if (unlikely(!(ctx->insns_flags & PPC_SEGMENT_64B))) {
> +            if (unlikely(!is_book3s_arch2x(ctx))) {
>                  gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
>                  tcg_temp_free(temp);
>                  tcg_temp_free(target);
> @@ -3913,7 +3913,7 @@ static void gen_rfi(DisasContext *ctx)
>      /* This instruction doesn't exist anymore on 64-bit server
>       * processors compliant with arch 2.x
>       */
> -    if (ctx->insns_flags & PPC_SEGMENT_64B) {
> +    if (is_book3s_arch2x(ctx)) {
>          gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
>          return;
>      }
> @@ -6535,8 +6535,7 @@ static void gen_msgclr(DisasContext *ctx)
>      GEN_PRIV;
>  #else
>      CHK_HV;
> -    /* 64-bit server processors compliant with arch 2.x */
> -    if (ctx->insns_flags & PPC_SEGMENT_64B) {
> +    if (is_book3s_arch2x(ctx)) {
>          gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
>      } else {
>          gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
> @@ -6550,8 +6549,7 @@ static void gen_msgsnd(DisasContext *ctx)
>      GEN_PRIV;
>  #else
>      CHK_HV;
> -    /* 64-bit server processors compliant with arch 2.x */
> -    if (ctx->insns_flags & PPC_SEGMENT_64B) {
> +    if (is_book3s_arch2x(ctx)) {
>          gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
>      } else {
>          gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
>
diff mbox series

Patch

diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 49d57469fb34..ad20584f268d 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1101,7 +1101,7 @@  clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
     tb_env = g_malloc0(sizeof(ppc_tb_t));
     env->tb_env = tb_env;
     tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
-    if (env->insns_flags & PPC_SEGMENT_64B) {
+    if (is_book3s_arch2x(env)) {
         /* All Book3S 64bit CPUs implement level based DEC logic */
         tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;
     }
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index fc12b4688e8c..070717758452 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2409,6 +2409,12 @@  enum {
 target_ulong cpu_read_xer(CPUPPCState *env);
 void cpu_write_xer(CPUPPCState *env, target_ulong xer);
 
+/*
+ * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
+ * have PPC_SEGMENT_64B.
+ */
+#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
+
 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
                                         target_ulong *cs_base, uint32_t *flags)
 {
diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h
index a2205e1044c9..c863abc0bfc3 100644
--- a/target/ppc/helper_regs.h
+++ b/target/ppc/helper_regs.h
@@ -152,7 +152,7 @@  static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
      * - 64-bit embedded implementations do not need any operation to be
      *   performed when PR is set.
      */
-    if ((env->insns_flags & PPC_SEGMENT_64B) && ((value >> MSR_PR) & 1)) {
+    if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) {
         value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
     }
 #endif
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d3aaa6482c6a..576210d901ad 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3755,7 +3755,7 @@  static void gen_bcond(DisasContext *ctx, int type)
              * arch 2.x, do implement a "test and decrement" logic instead,
              * as described in their respective UMs.
              */
-            if (unlikely(!(ctx->insns_flags & PPC_SEGMENT_64B))) {
+            if (unlikely(!is_book3s_arch2x(ctx))) {
                 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
                 tcg_temp_free(temp);
                 tcg_temp_free(target);
@@ -3913,7 +3913,7 @@  static void gen_rfi(DisasContext *ctx)
     /* This instruction doesn't exist anymore on 64-bit server
      * processors compliant with arch 2.x
      */
-    if (ctx->insns_flags & PPC_SEGMENT_64B) {
+    if (is_book3s_arch2x(ctx)) {
         gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
         return;
     }
@@ -6535,8 +6535,7 @@  static void gen_msgclr(DisasContext *ctx)
     GEN_PRIV;
 #else
     CHK_HV;
-    /* 64-bit server processors compliant with arch 2.x */
-    if (ctx->insns_flags & PPC_SEGMENT_64B) {
+    if (is_book3s_arch2x(ctx)) {
         gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
     } else {
         gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
@@ -6550,8 +6549,7 @@  static void gen_msgsnd(DisasContext *ctx)
     GEN_PRIV;
 #else
     CHK_HV;
-    /* 64-bit server processors compliant with arch 2.x */
-    if (ctx->insns_flags & PPC_SEGMENT_64B) {
+    if (is_book3s_arch2x(ctx)) {
         gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
     } else {
         gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);