ARM: dts: dra7: Add properties to enable PCIe x2 lane mode
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Message ID 20190325094525.362-1-kishon@ti.com
State New
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Series
  • ARM: dts: dra7: Add properties to enable PCIe x2 lane mode
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Commit Message

Kishon Vijay Abraham I March 25, 2019, 9:45 a.m. UTC
ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable
PCIe x2 lane mode are added here.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 2 ++
 1 file changed, 2 insertions(+)

Comments

Tony Lindgren April 9, 2019, 2:59 p.m. UTC | #1
* Kishon Vijay Abraham I <kishon@ti.com> [190325 02:46]:
> ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable
> PCIe x2 lane mode are added here.

Applying into omap-for-v5.2/dt thanks.

Tony

Patch
diff mbox series

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 2bc9add8b7a5..d87e932f45bd 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -193,6 +193,7 @@ 
 				ti,hwmods = "pcie1";
 				phys = <&pcie1_phy>;
 				phy-names = "pcie-phy0";
+				ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
 				interrupt-map-mask = <0 0 0 7>;
 				interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 						<0 0 0 2 &pcie1_intc 2>,
@@ -218,6 +219,7 @@ 
 				phys = <&pcie1_phy>;
 				phy-names = "pcie-phy0";
 				ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
+				ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
 				status = "disabled";
 			};
 		};