@@ -382,5 +382,47 @@
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
+
+ cam_smem: cam_smem {
+ compatible = "mediatek,mt8183-cam_smem";
+ mediatek,larb = <&larb3>,
+ <&larb6>;
+ iommus = <&iommu M4U_PORT_CAM_LSCI0>,
+ <&iommu M4U_PORT_CAM_LSCI1>,
+ <&iommu M4U_PORT_CAM_BPCI>;
+ };
+
+ camisp: camisp@1a000000 {
+ compatible = "mediatek,mt8183-camisp", "syscon";
+ reg = <0 0x1a000000 0 0x1000>,
+ <0 0x1a003000 0 0x1000>,
+ <0 0x1a004000 0 0x2000>,
+ <0 0x1a006000 0 0x2000>;
+ reg-names = "camisp",
+ "cam1",
+ "cam2",
+ "cam3";
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "cam1",
+ "cam2",
+ "cam3";
+ iommus = <&iommu M4U_PORT_CAM_LSCI0>,
+ <&iommu M4U_PORT_CAM_LSCI1>,
+ <&iommu M4U_PORT_CAM_BPCI>;
+ #clock-cells = <1>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_CAM>;
+ /* Camera CCF */
+ clocks = <&camsys CLK_CAM_CAM>,
+ <&camsys CLK_CAM_CAMTG>;
+ clock-names = "CAMSYS_CAM_CGPDN",
+ "CAMSYS_CAMTG_CGPDN";
+ mediatek,larb = <&larb3>,
+ <&larb6>;
+ mediatek,scp = <&scp>;
+ smem_device = <&cam_smem>;
+ };
+
};
};
Add nodes for Pass 1 unit of Mediatek's camera ISP system. Pass 1 unit embedded in Mediatek SoCs, works with the co-processor to process image signal from the image sensor and output RAW data. Signed-off-by: Jungo Lin <jungo.lin@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 42 ++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+)