diff mbox series

[v7,10/16] drm/i915/icl: Add ICL Plane Degamma Register definition

Message ID 1553804174-2651-11-git-send-email-uma.shankar@intel.com (mailing list archive)
State New, archived
Headers show
Series Add Plane Color Properties | expand

Commit Message

Shankar, Uma March 28, 2019, 8:16 p.m. UTC
Add register definitions for ICL Plane Degamma.

v2: Fixed register definitions for Degamma Index, spotted
by Matt Roper.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 42 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e896798..ed02963 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10181,6 +10181,48 @@  enum skl_power_gate {
 #define PLANE_GAMC16(pipe, plane, i) _MMIO_PLANE_GAMC16(plane, i, \
 				_PLANE_GAMC16_1(pipe), _PLANE_GAMC16_2(pipe))
 
+/* Plane Color Register for Gen11+ */
+/* Plane Degamma Registers */
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A	0x701D0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B	0x711D0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A	0x702D0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B	0x712D0
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B)
+
+#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i)	_MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe),\
+									 _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_INDEX_4_A		0x704D0
+#define _PLANE_PRE_CSC_GAMC_INDEX_4_B		0x714D0
+#define _PLANE_PRE_CSC_GAMC_INDEX_5_A		0x705D0
+#define _PLANE_PRE_CSC_GAMC_INDEX_5_B		0x715D0
+#define _PLANE_PRE_CSC_GAMC_INDEX_4(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_4_A, _PLANE_PRE_CSC_GAMC_INDEX_4_B)
+#define _PLANE_PRE_CSC_GAMC_INDEX_5(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_5_A, _PLANE_PRE_CSC_GAMC_INDEX_5_B)
+
+#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i)	_MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_4(pipe),\
+									 _PLANE_PRE_CSC_GAMC_INDEX_5(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A	0x701D4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B	0x711D4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A	0x702D4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B	0x712D4
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B)
+
+#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i)	_MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe),\
+									 _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe))
+
+#define _PLANE_PRE_CSC_GAMC_DATA_4_A		0x704D4
+#define _PLANE_PRE_CSC_GAMC_DATA_4_B		0x714D4
+#define _PLANE_PRE_CSC_GAMC_DATA_5_A		0x705D4
+#define _PLANE_PRE_CSC_GAMC_DATA_5_B		0x715D4
+#define _PLANE_PRE_CSC_GAMC_DATA_4(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_4_A, _PLANE_PRE_CSC_GAMC_DATA_4_B)
+#define _PLANE_PRE_CSC_GAMC_DATA_5(pipe)	_PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_5_A, _PLANE_PRE_CSC_GAMC_DATA_5_B)
+
+#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i)	_MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_4(pipe),\
+									 _PLANE_PRE_CSC_GAMC_DATA_5(pipe))
+
 /* pipe CSC & degamma/gamma LUTs on CHV */
 #define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)
 #define _CGM_PIPE_A_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x67904)