| Message ID | 20190328210505.10429-5-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Finish the GAMMA_LUT stuff | expand |
On Thu, Mar 28, 2019 at 11:05:03PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Plop in support for 10bit LUT on ilk/snb. > > There is no split gamma mode on these platforms, so we have > to choose between degamma and gamma. That could be a runtime choice > but for now let's just advertize the gamma as having 1024 entries. > We'll also keep the ctm hidden for now. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> I also glanced through patches 5 and 6 and didn't notice anything obviously wrong, but I'm not sure how to find bspec-level information for those platforms. Matt > --- > drivers/gpu/drm/i915/i915_pci.c | 4 +++ > drivers/gpu/drm/i915/i915_reg.h | 9 ++++++ > drivers/gpu/drm/i915/intel_color.c | 44 ++++++++++++++++++++++++++---- > 3 files changed, 51 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index 385056752939..0971eee4a4d1 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -116,6 +116,8 @@ > [PIPE_C] = IVB_CURSOR_C_OFFSET, \ > } > > +#define ILK_COLORS \ > + .color = { .gamma_lut_size = 1024 } > #define IVB_COLORS \ > .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } > #define CHV_COLORS \ > @@ -325,6 +327,7 @@ static const struct intel_device_info intel_gm45_info = { > .has_rc6 = 0, \ > I9XX_PIPE_OFFSETS, \ > I9XX_CURSOR_OFFSETS, \ > + ILK_COLORS, \ > GEN_DEFAULT_PAGE_SIZES > > static const struct intel_device_info intel_ironlake_d_info = { > @@ -353,6 +356,7 @@ static const struct intel_device_info intel_ironlake_m_info = { > .ppgtt_size = 31, \ > I9XX_PIPE_OFFSETS, \ > I9XX_CURSOR_OFFSETS, \ > + ILK_COLORS, \ > GEN_DEFAULT_PAGE_SIZES > > #define SNB_D_PLATFORM \ > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index eb7e93354cfe..f6a5d8f11368 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7209,6 +7209,15 @@ enum { > #define _LGC_PALETTE_B 0x4a800 > #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) > > +/* ilk/snb precision palette */ > +#define _PREC_PALETTE_A 0x4b000 > +#define _PREC_PALETTE_B 0x4c000 > +#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) > + > +#define _PREC_PIPEAGCMAX 0x4d000 > +#define _PREC_PIPEBGCMAX 0x4d010 > +#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) > + > #define _GAMMA_MODE_A 0x4a480 > #define _GAMMA_MODE_B 0x4ac80 > #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c > index 70a71c92e3e5..8e03f066adf7 100644 > --- a/drivers/gpu/drm/i915/intel_color.c > +++ b/drivers/gpu/drm/i915/intel_color.c > @@ -468,6 +468,29 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state) > ilk_load_csc_matrix(crtc_state); > } > > +static void ilk_load_lut_10(struct intel_crtc *crtc, > + const struct drm_property_blob *blob) > +{ > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + const struct drm_color_lut *lut = blob->data; > + int i, lut_size = drm_color_lut_size(blob); > + enum pipe pipe = crtc->pipe; > + > + for (i = 0; i < lut_size; i++) > + I915_WRITE_FW(PREC_PALETTE(pipe, i), ilk_lut_10(&lut[i])); > +} > + > +static void ilk_load_luts(const struct intel_crtc_state *crtc_state) > +{ > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > + const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; > + > + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) > + i9xx_load_luts(crtc_state); > + else > + ilk_load_lut_10(crtc, gamma_lut); > +} > + > /* > * IVB/HSW Bspec / PAL_PREC_INDEX: > * "Restriction : Index auto increment mode is not > @@ -961,6 +984,15 @@ static int chv_color_check(struct intel_crtc_state *crtc_state) > return 0; > } > > +static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state) > +{ > + if (!crtc_state->gamma_enable || > + crtc_state_is_legacy_gamma(crtc_state)) > + return GAMMA_MODE_MODE_8BIT; > + else > + return GAMMA_MODE_MODE_10BIT; > +} > + > static int ilk_color_check(struct intel_crtc_state *crtc_state) > { > int ret; > @@ -980,8 +1012,7 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state) > */ > crtc_state->csc_enable = false; > > - /* We don't expose fancy gamma modes on ilk/snb currently */ > - crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; > + crtc_state->gamma_mode = ilk_gamma_mode(crtc_state); > > crtc_state->csc_mode = 0; > > @@ -1178,14 +1209,15 @@ void intel_color_init(struct intel_crtc *crtc) > else if (INTEL_GEN(dev_priv) >= 7) > dev_priv->display.load_luts = ivb_load_luts; > else > - dev_priv->display.load_luts = i9xx_load_luts; > + dev_priv->display.load_luts = ilk_load_luts; > } > > - /* Enable color management support when we have degamma & gamma LUTs. */ > - if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 && > + /* Enable color management support when we have degamma and/or gamma LUT. */ > + if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 || > INTEL_INFO(dev_priv)->color.gamma_lut_size != 0) > drm_crtc_enable_color_mgmt(&crtc->base, > INTEL_INFO(dev_priv)->color.degamma_lut_size, > - true, > + INTEL_INFO(dev_priv)->color.degamma_lut_size && > + INTEL_INFO(dev_priv)->color.gamma_lut_size, > INTEL_INFO(dev_priv)->color.gamma_lut_size); > } > -- > 2.19.2 >
Op 28-03-2019 om 22:05 schreef Ville Syrjala: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Plop in support for 10bit LUT on ilk/snb. > > There is no split gamma mode on these platforms, so we have > to choose between degamma and gamma. That could be a runtime choice > but for now let's just advertize the gamma as having 1024 entries. > We'll also keep the ctm hidden for now. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_pci.c | 4 +++ > drivers/gpu/drm/i915/i915_reg.h | 9 ++++++ > drivers/gpu/drm/i915/intel_color.c | 44 ++++++++++++++++++++++++++---- > 3 files changed, 51 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index 385056752939..0971eee4a4d1 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -116,6 +116,8 @@ > [PIPE_C] = IVB_CURSOR_C_OFFSET, \ > } > > +#define ILK_COLORS \ > + .color = { .gamma_lut_size = 1024 } > #define IVB_COLORS \ > .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } > #define CHV_COLORS \ > @@ -325,6 +327,7 @@ static const struct intel_device_info intel_gm45_info = { > .has_rc6 = 0, \ > I9XX_PIPE_OFFSETS, \ > I9XX_CURSOR_OFFSETS, \ > + ILK_COLORS, \ > GEN_DEFAULT_PAGE_SIZES > > static const struct intel_device_info intel_ironlake_d_info = { > @@ -353,6 +356,7 @@ static const struct intel_device_info intel_ironlake_m_info = { > .ppgtt_size = 31, \ > I9XX_PIPE_OFFSETS, \ > I9XX_CURSOR_OFFSETS, \ > + ILK_COLORS, \ > GEN_DEFAULT_PAGE_SIZES > > #define SNB_D_PLATFORM \ > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index eb7e93354cfe..f6a5d8f11368 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7209,6 +7209,15 @@ enum { > #define _LGC_PALETTE_B 0x4a800 > #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) > > +/* ilk/snb precision palette */ > +#define _PREC_PALETTE_A 0x4b000 > +#define _PREC_PALETTE_B 0x4c000 > +#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) > + > +#define _PREC_PIPEAGCMAX 0x4d000 > +#define _PREC_PIPEBGCMAX 0x4d010 > +#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) > + > #define _GAMMA_MODE_A 0x4a480 > #define _GAMMA_MODE_B 0x4ac80 > #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c > index 70a71c92e3e5..8e03f066adf7 100644 > --- a/drivers/gpu/drm/i915/intel_color.c > +++ b/drivers/gpu/drm/i915/intel_color.c > @@ -468,6 +468,29 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state) > ilk_load_csc_matrix(crtc_state); > } > > +static void ilk_load_lut_10(struct intel_crtc *crtc, > + const struct drm_property_blob *blob) > +{ > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + const struct drm_color_lut *lut = blob->data; > + int i, lut_size = drm_color_lut_size(blob); > + enum pipe pipe = crtc->pipe; > + > + for (i = 0; i < lut_size; i++) > + I915_WRITE_FW(PREC_PALETTE(pipe, i), ilk_lut_10(&lut[i])); > +} > + > +static void ilk_load_luts(const struct intel_crtc_state *crtc_state) > +{ > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > + const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; > + > + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) > + i9xx_load_luts(crtc_state); > + else > + ilk_load_lut_10(crtc, gamma_lut); > +} > + > /* > * IVB/HSW Bspec / PAL_PREC_INDEX: > * "Restriction : Index auto increment mode is not > @@ -961,6 +984,15 @@ static int chv_color_check(struct intel_crtc_state *crtc_state) > return 0; > } > > +static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state) > +{ > + if (!crtc_state->gamma_enable || > + crtc_state_is_legacy_gamma(crtc_state)) > + return GAMMA_MODE_MODE_8BIT; > + else > + return GAMMA_MODE_MODE_10BIT; > +} > + > static int ilk_color_check(struct intel_crtc_state *crtc_state) > { > int ret; > @@ -980,8 +1012,7 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state) > */ > crtc_state->csc_enable = false; > > - /* We don't expose fancy gamma modes on ilk/snb currently */ > - crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; > + crtc_state->gamma_mode = ilk_gamma_mode(crtc_state); > > crtc_state->csc_mode = 0; > > @@ -1178,14 +1209,15 @@ void intel_color_init(struct intel_crtc *crtc) > else if (INTEL_GEN(dev_priv) >= 7) > dev_priv->display.load_luts = ivb_load_luts; > else > - dev_priv->display.load_luts = i9xx_load_luts; > + dev_priv->display.load_luts = ilk_load_luts; > } > > - /* Enable color management support when we have degamma & gamma LUTs. */ > - if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 && > + /* Enable color management support when we have degamma and/or gamma LUT. */ > + if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 || > INTEL_INFO(dev_priv)->color.gamma_lut_size != 0) > drm_crtc_enable_color_mgmt(&crtc->base, > INTEL_INFO(dev_priv)->color.degamma_lut_size, > - true, > + INTEL_INFO(dev_priv)->color.degamma_lut_size && > + INTEL_INFO(dev_priv)->color.gamma_lut_size, > INTEL_INFO(dev_priv)->color.gamma_lut_size); > } Maybe nitpicking, but ctm seems to only be enabled when degamma_lut_size is set. It could probably be used as bool has_ctm = degamma_lut_size. Furthermore it's harmless to call drm_crtc_enable_color_mgmt() unconditionally here instead of patch 6; calling it with 0 gamma and degamma size and has_ctm = false is a noop. :) Otherwise patch series looks good. For all patches except 2: Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 385056752939..0971eee4a4d1 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -116,6 +116,8 @@ [PIPE_C] = IVB_CURSOR_C_OFFSET, \ } +#define ILK_COLORS \ + .color = { .gamma_lut_size = 1024 } #define IVB_COLORS \ .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } #define CHV_COLORS \ @@ -325,6 +327,7 @@ static const struct intel_device_info intel_gm45_info = { .has_rc6 = 0, \ I9XX_PIPE_OFFSETS, \ I9XX_CURSOR_OFFSETS, \ + ILK_COLORS, \ GEN_DEFAULT_PAGE_SIZES static const struct intel_device_info intel_ironlake_d_info = { @@ -353,6 +356,7 @@ static const struct intel_device_info intel_ironlake_m_info = { .ppgtt_size = 31, \ I9XX_PIPE_OFFSETS, \ I9XX_CURSOR_OFFSETS, \ + ILK_COLORS, \ GEN_DEFAULT_PAGE_SIZES #define SNB_D_PLATFORM \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index eb7e93354cfe..f6a5d8f11368 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7209,6 +7209,15 @@ enum { #define _LGC_PALETTE_B 0x4a800 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) +/* ilk/snb precision palette */ +#define _PREC_PALETTE_A 0x4b000 +#define _PREC_PALETTE_B 0x4c000 +#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) + +#define _PREC_PIPEAGCMAX 0x4d000 +#define _PREC_PIPEBGCMAX 0x4d010 +#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) + #define _GAMMA_MODE_A 0x4a480 #define _GAMMA_MODE_B 0x4ac80 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 70a71c92e3e5..8e03f066adf7 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -468,6 +468,29 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state) ilk_load_csc_matrix(crtc_state); } +static void ilk_load_lut_10(struct intel_crtc *crtc, + const struct drm_property_blob *blob) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_color_lut *lut = blob->data; + int i, lut_size = drm_color_lut_size(blob); + enum pipe pipe = crtc->pipe; + + for (i = 0; i < lut_size; i++) + I915_WRITE_FW(PREC_PALETTE(pipe, i), ilk_lut_10(&lut[i])); +} + +static void ilk_load_luts(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut; + + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) + i9xx_load_luts(crtc_state); + else + ilk_load_lut_10(crtc, gamma_lut); +} + /* * IVB/HSW Bspec / PAL_PREC_INDEX: * "Restriction : Index auto increment mode is not @@ -961,6 +984,15 @@ static int chv_color_check(struct intel_crtc_state *crtc_state) return 0; } +static u32 ilk_gamma_mode(const struct intel_crtc_state *crtc_state) +{ + if (!crtc_state->gamma_enable || + crtc_state_is_legacy_gamma(crtc_state)) + return GAMMA_MODE_MODE_8BIT; + else + return GAMMA_MODE_MODE_10BIT; +} + static int ilk_color_check(struct intel_crtc_state *crtc_state) { int ret; @@ -980,8 +1012,7 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state) */ crtc_state->csc_enable = false; - /* We don't expose fancy gamma modes on ilk/snb currently */ - crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; + crtc_state->gamma_mode = ilk_gamma_mode(crtc_state); crtc_state->csc_mode = 0; @@ -1178,14 +1209,15 @@ void intel_color_init(struct intel_crtc *crtc) else if (INTEL_GEN(dev_priv) >= 7) dev_priv->display.load_luts = ivb_load_luts; else - dev_priv->display.load_luts = i9xx_load_luts; + dev_priv->display.load_luts = ilk_load_luts; } - /* Enable color management support when we have degamma & gamma LUTs. */ - if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 && + /* Enable color management support when we have degamma and/or gamma LUT. */ + if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 || INTEL_INFO(dev_priv)->color.gamma_lut_size != 0) drm_crtc_enable_color_mgmt(&crtc->base, INTEL_INFO(dev_priv)->color.degamma_lut_size, - true, + INTEL_INFO(dev_priv)->color.degamma_lut_size && + INTEL_INFO(dev_priv)->color.gamma_lut_size, INTEL_INFO(dev_priv)->color.gamma_lut_size); }