From patchwork Tue Apr 2 23:30:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Harrison X-Patchwork-Id: 10882465 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3F57E139A for ; Tue, 2 Apr 2019 23:30:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1A79F28895 for ; Tue, 2 Apr 2019 23:30:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0E3CA289A2; Tue, 2 Apr 2019 23:30:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 06F3528895 for ; Tue, 2 Apr 2019 23:30:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 364886E44A; Tue, 2 Apr 2019 23:30:09 +0000 (UTC) X-Original-To: Intel-GFX@lists.freedesktop.org Delivered-To: Intel-GFX@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 202516E44A for ; Tue, 2 Apr 2019 23:30:07 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Apr 2019 16:30:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,302,1549958400"; d="scan'208";a="146074620" Received: from relo-linux-5.ra.intel.com ([10.54.133.84]) by FMSMGA003.fm.intel.com with ESMTP; 02 Apr 2019 16:30:01 -0700 From: John.C.Harrison@Intel.com To: Intel-GFX@Lists.FreeDesktop.Org Date: Tue, 2 Apr 2019 16:30:01 -0700 Message-Id: <20190402233001.27352-1-John.C.Harrison@Intel.com> X-Mailer: git-send-email 2.21.0.5.gaeb582a983 In-Reply-To: <20190401230707.10885-1-John.C.Harrison@Intel.com> References: <20190401230707.10885-1-John.C.Harrison@Intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 0/11 v4] drm/i915: Extra media engines for ATS X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: John Harrison ATS has lots of extra media engines. This series adds support for them. Note, a recent GuC FW is required - 32.0.3 is known to be good. Version 31.0.1 causes a hang when i915 initialised the fifth VCS engine. v2: Clean up the I915_MAX_ENGINES define. Make assumptions about ATS engine counts. [Tvrtko Ursulin] v3: Rebase to a new location within the internal history and add a NOT_UPSTREAM patch to disable the extra engines if the GuC FW in use is too old to support them. [Daniele]. v4: Tweaks to GuC FW test (for module param overrides) and to interrupt enabling (to support fused parts). [Daniele] Signed-off-by: John Harrison CC: Daniele Ceraolo Spurio CC: Tvrtko Ursulin --- baseline: 32a1e283d330638d2e5de8f89a9ff7c8512b75e8 pile-commit: 603f996d0b32c3733f4ce4e7263e9f40e0d263ce range-diff: -: ------------ > 142: ce1f037b197f drm/i915/selftests: Allow for larger engine counts -: ------------ > 143: 61e8501f5afe drm/i915: Extra media engines for ATS - Part 1 (engine definitions) -: ------------ > 144: eaf383e48944 drm/i915: Extra media engines for ATS - Part 2 (interrupts) -: ------------ > 145: 7d107e0cde94 drm/i915: Extra media engines for ATS - Part 3 (reset) -: ------------ > 146: 9d3d03cbd52d drm/i915: Extra media engines for ATS - Part 4 (FW) -: ------------ > 147: e37f175dd42e drm/i915: Extra media engines for ATS - Part 5 (UAPI) 217: af2ca7c68d46 ! 223: bfbff755e80c drm/i915/ats: ATS has MMIO doorbells -: ------------ > 239: facf506a7805 NOT_UPSTREAM: drm/i915: Disable extra engines on older GuC FW 275: 0ceb5bac58a5 < -: ------------ drm/i915/ats: Disable all display device information capabilities -: ------------ > 282: f0213ad8ede3 drm/i915/ats: Disable all display device information capabilities 301: 643dcaa8783f ! 308: 960d8a3acefe drm/i915/guc: Support for VFPF relay messages 317: 2a3a78301cee ! 324: 3ccd2e3fca85 drm/i915: Add has_remote_tiles to device info series | 7 + ...M-drm-i915-Disable-extra-engines-on-older.patch | 80 ++++++++ ...-i915-Add-has_remote_tiles-to-device-info.patch | 4 +- ...tra-media-engines-for-ATS-Part-1-engine-d.patch | 218 +++++++++++++++++++++ ...tra-media-engines-for-ATS-Part-2-interrup.patch | 97 +++++++++ ...-Extra-media-engines-for-ATS-Part-3-reset.patch | 54 +++++ ...915-Extra-media-engines-for-ATS-Part-4-FW.patch | 110 +++++++++++ ...5-Extra-media-engines-for-ATS-Part-5-UAPI.patch | 30 +++ 0001-drm-i915-ats-ATS-has-MMIO-doorbells.patch | 4 +- ...s-Disable-all-display-device-information-.patch | 8 +- ...-i915-guc-Support-for-VFPF-relay-messages.patch | 4 +- ...-selftests-Allow-for-larger-engine-counts.patch | 85 ++++++++ 12 files changed, 691 insertions(+), 10 deletions(-) -- git-pile 0.91 diff --git a/series b/series index e8645e80dbf9..4a072408dad2 100644 --- a/series +++ b/series @@ -141,6 +141,12 @@ 0001-drm-i915-ats-ack-intr-through-master-control.patch 0001-FIXME-drm-i915-ats-context-status-and-descriptor-cha.patch 0001-drm-i915-ats-Handle-ATS-VDBOX-VEBOX-fusing-register.patch +0001-drm-i915-selftests-Allow-for-larger-engine-counts.patch +0001-drm-i915-Extra-media-engines-for-ATS-Part-1-engine-d.patch +0001-drm-i915-Extra-media-engines-for-ATS-Part-2-interrup.patch +0001-drm-i915-Extra-media-engines-for-ATS-Part-3-reset.patch +0001-drm-i915-Extra-media-engines-for-ATS-Part-4-FW.patch +0001-drm-i915-Extra-media-engines-for-ATS-Part-5-UAPI.patch 0001-NOTUPSTREAM-drm-i915-perf-Enable-large-OA-buffer-sup.patch 0001-NOTUPSTREAM-drm-i915-perf-complete-programming-white.patch 0001-drm-i915-support-1G-pages-for-the-48b-PPGTT.patch @@ -232,6 +238,7 @@ 0001-drm-i915-dg1-add-initial-DG-1-definitions.patch 0001-drm-i915-dg1-Add-DG1-PCI-IDs.patch 0001-DRM_INTEL_INTERNAL_PLATFORM_POINT-dg1.patch +0001-NOT_UPSTREAM-drm-i915-Disable-extra-engines-on-older.patch 0001-NOT_UPSTREAM-drm-i915-tgl-ack-master-control-on-all-.patch 0001-NOT_UPSTREAM-drm-i915-guc-add-H2G-to-ring-doorbells.patch 0001-NOT-UPSTREAM-drm-i915-guc-Workaround-ATS-GuC-31.0.0-.patch diff --git a/0001-NOT_UPSTREAM-drm-i915-Disable-extra-engines-on-older.patch b/0001-NOT_UPSTREAM-drm-i915-Disable-extra-engines-on-older.patch new file mode 100644 index 000000000000..05a7a12ca66c --- /dev/null +++ b/0001-NOT_UPSTREAM-drm-i915-Disable-extra-engines-on-older.patch @@ -0,0 +1,80 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: John Harrison +Date: Mon, 1 Apr 2019 12:24:50 -0700 +Subject: [PATCH] NOT_UPSTREAM: drm/i915: Disable extra engines on older GuC FW + +The current GuC FW release (31.0.1) dies when presented with too many +media engines. The issue was fixed by 32.0.3 (which is the next FW the +driver is intending to switch to). It is desirable to merge the the +patches which allow use of the new engines before the new GuC FW +patches can be merged. E.g. for running in non-GuC mode and/or running +with a locally patched driver for the newer FW. Hence this patch +disables the extra engines if the newer FW is not found. + +v2: Cope with GuC FWs loaded via the module param (by just ignoring it +and warning the user). [Daniele] + +Signed-off-by: John Harrison +CC: Daniele Ceraolo Spurio +--- + drivers/gpu/drm/i915/intel_device_info.c | 24 ++++++++++++++++++++++++ + drivers/gpu/drm/i915/intel_guc_fw.c | 1 + + drivers/gpu/drm/i915/intel_uc_fw.h | 1 + + 3 files changed, 26 insertions(+) + +diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c +--- a/drivers/gpu/drm/i915/intel_device_info.c ++++ b/drivers/gpu/drm/i915/intel_device_info.c +@@ -945,6 +945,30 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) + vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> + GEN11_GT_VEBOX_DISABLE_SHIFT; + ++ if (USES_GUC_SUBMISSION(dev_priv)) { ++ struct intel_guc *guc = &dev_priv->guc; ++ struct intel_uc_fw *guc_fw = &guc->fw; ++ u32 guc_ver, guc_req; ++ ++ /* GuC < 32.0.3 barfs on too many media engines */ ++ /* NB: *_ver_found is not available yet so need to use _ver_wanted. */ ++ ++ if (!guc_fw->major_ver_wanted && !guc_fw->minor_ver_wanted) { ++ DRM_INFO("GuC FW version unknown (overridden by module param?).\n"); ++ DRM_INFO("NB: FW earlier than 32.0.3 may break VCS4-7 and VECS2-3!\n"); ++ } else { ++ guc_ver = (guc_fw->major_ver_wanted << 16) | ++ (guc_fw->minor_ver_wanted << 8) | ++ guc_fw->patch_ver_wanted; ++ ++ guc_req = (32 << 16) | (0 << 8) | 3; ++ if (guc_ver < guc_req) { ++ vdbox_mask &= 0xF; ++ vebox_mask &= 0x3; ++ } ++ } ++ } ++ + for (i = 0; i < I915_MAX_VCS; i++) { + if (!HAS_ENGINE(dev_priv, _VCS(i))) + continue; +diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c +--- a/drivers/gpu/drm/i915/intel_guc_fw.c ++++ b/drivers/gpu/drm/i915/intel_guc_fw.c +@@ -98,6 +98,7 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw) + guc_fw->path = ATS_GUC_FIRMWARE_PATH; + guc_fw->major_ver_wanted = ATS_GUC_FW_MAJOR; + guc_fw->minor_ver_wanted = ATS_GUC_FW_MINOR; ++ guc_fw->patch_ver_wanted = ATS_GUC_FW_PATCH; + } else if (IS_TIGERLAKE(i915)) { + guc_fw->path = TGL_GUC_FIRMWARE_PATH; + guc_fw->major_ver_wanted = TGL_GUC_FW_MAJOR; +diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/intel_uc_fw.h +--- a/drivers/gpu/drm/i915/intel_uc_fw.h ++++ b/drivers/gpu/drm/i915/intel_uc_fw.h +@@ -62,6 +62,7 @@ struct intel_uc_fw { + */ + u16 major_ver_wanted; + u16 minor_ver_wanted; ++ u16 patch_ver_wanted; + u16 major_ver_found; + u16 minor_ver_found; + diff --git a/0001-drm-i915-Add-has_remote_tiles-to-device-info.patch b/0001-drm-i915-Add-has_remote_tiles-to-device-info.patch index 25d2b969eef0..ed470e5c95b3 100644 --- a/0001-drm-i915-Add-has_remote_tiles-to-device-info.patch +++ b/0001-drm-i915-Add-has_remote_tiles-to-device-info.patch @@ -34,8 +34,8 @@ diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c .has_guc_mmio_db = 1, + .has_remote_tiles = 1, .engine_mask = - BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VECS1) | BIT(VCS0) | - BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | BIT(CCS0), + BIT(RCS0) | BIT(BCS0) | + BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h diff --git a/0001-drm-i915-Extra-media-engines-for-ATS-Part-1-engine-d.patch b/0001-drm-i915-Extra-media-engines-for-ATS-Part-1-engine-d.patch new file mode 100644 index 000000000000..e407230dacbe --- /dev/null +++ b/0001-drm-i915-Extra-media-engines-for-ATS-Part-1-engine-d.patch @@ -0,0 +1,218 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: John Harrison +Date: Fri, 22 Mar 2019 16:22:19 -0700 +Subject: [PATCH] drm/i915: Extra media engines for ATS - Part 1 (engine + definitions) + +ATS has lots of extra media engines. This patch adds the basic +definitions for them. + +Also, add a sentinel to the engine id enum. That way there is no need +to know which engine is the last in the list. + +v2: Clean up I915_MAX_ENGINES - it is now the sentinel enum value in +the engine id list rather than a separate define in a separate header. +[Tvrtko Ursulin] + +Signed-off-by: John Harrison +Cc: Tvrtko Ursulin +--- + drivers/gpu/drm/i915/i915_gem.h | 2 - + drivers/gpu/drm/i915/i915_reg.h | 8 ++- + drivers/gpu/drm/i915/i915_reset.c | 2 - + drivers/gpu/drm/i915/intel_engine_cs.c | 56 +++++++++++++++++++++ + drivers/gpu/drm/i915/intel_engine_types.h | 14 ++++-- + drivers/gpu/drm/i915/intel_guc.h | 1 + + drivers/gpu/drm/i915/intel_guc_submission.h | 2 +- + 7 files changed, 76 insertions(+), 9 deletions(-) + +diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h +--- a/drivers/gpu/drm/i915/i915_gem.h ++++ b/drivers/gpu/drm/i915/i915_gem.h +@@ -73,8 +73,6 @@ struct drm_i915_private; + #define GEM_TRACE_DUMP_ON(expr) BUILD_BUG_ON_INVALID(expr) + #endif + +-#define I915_NUM_ENGINES 9 +- + #define I915_GEM_IDLE_TIMEOUT (HZ / 5) + + void i915_gem_park(struct drm_i915_private *i915); +diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -294,7 +294,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) + + #define OTHER_GUC_INSTANCE 0 + #define OTHER_GTPM_INSTANCE 1 +-#define MAX_ENGINE_INSTANCE 3 ++#define MAX_ENGINE_INSTANCE 7 + + /* PCI config space */ + +@@ -2536,9 +2536,15 @@ enum i915_power_well_id { + #define GEN11_BSD2_RING_BASE 0x1c4000 + #define GEN11_BSD3_RING_BASE 0x1d0000 + #define GEN11_BSD4_RING_BASE 0x1d4000 ++#define GEN12_BSD5_RING_BASE 0x1e0000 ++#define GEN12_BSD6_RING_BASE 0x1e4000 ++#define GEN12_BSD7_RING_BASE 0x1f0000 ++#define GEN12_BSD8_RING_BASE 0x1f4000 + #define VEBOX_RING_BASE 0x1a000 + #define GEN11_VEBOX_RING_BASE 0x1c8000 + #define GEN11_VEBOX2_RING_BASE 0x1d8000 ++#define GEN12_VEBOX3_RING_BASE 0x1e8000 ++#define GEN12_VEBOX4_RING_BASE 0x1f8000 + #define GEN12_COMPUTE0_RING_BASE 0x1a000 + #define BLT_RING_BASE 0x22000 + #define RING_TAIL(base) _MMIO((base) + 0x30) +diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c +--- a/drivers/gpu/drm/i915/i915_reset.c ++++ b/drivers/gpu/drm/i915/i915_reset.c +@@ -448,8 +448,6 @@ static int gen11_reset_engines(struct drm_i915_private *i915, + u32 hw_mask; + int ret; + +- BUILD_BUG_ON(CCS0 + 1 != I915_NUM_ENGINES); +- + if (engine_mask == ALL_ENGINES) { + hw_mask = GEN11_GRDOM_FULL; + } else { +diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c +--- a/drivers/gpu/drm/i915/intel_engine_cs.c ++++ b/drivers/gpu/drm/i915/intel_engine_cs.c +@@ -158,6 +158,42 @@ static const struct engine_info intel_engines[] = { + { .gen = 11, .base = GEN11_BSD4_RING_BASE } + }, + }, ++ [VCS4] = { ++ .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */ ++ .class = VIDEO_DECODE_CLASS, ++ .guc_class = GUC_VIDEO_CLASS, ++ .instance = 4, ++ .mmio_bases = { ++ { .gen = 11, .base = GEN12_BSD5_RING_BASE } ++ }, ++ }, ++ [VCS5] = { ++ .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */ ++ .class = VIDEO_DECODE_CLASS, ++ .guc_class = GUC_VIDEO_CLASS, ++ .instance = 5, ++ .mmio_bases = { ++ { .gen = 12, .base = GEN12_BSD6_RING_BASE } ++ }, ++ }, ++ [VCS6] = { ++ .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */ ++ .class = VIDEO_DECODE_CLASS, ++ .guc_class = GUC_VIDEO_CLASS, ++ .instance = 6, ++ .mmio_bases = { ++ { .gen = 12, .base = GEN12_BSD7_RING_BASE } ++ }, ++ }, ++ [VCS7] = { ++ .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */ ++ .class = VIDEO_DECODE_CLASS, ++ .guc_class = GUC_VIDEO_CLASS, ++ .instance = 7, ++ .mmio_bases = { ++ { .gen = 12, .base = GEN12_BSD8_RING_BASE } ++ }, ++ }, + [VECS0] = { + .hw_id = VECS0_HW, + .class = VIDEO_ENHANCEMENT_CLASS, +@@ -177,6 +213,24 @@ static const struct engine_info intel_engines[] = { + { .gen = 11, .base = GEN11_VEBOX2_RING_BASE } + }, + }, ++ [VECS2] = { ++ .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */ ++ .class = VIDEO_ENHANCEMENT_CLASS, ++ .guc_class = GUC_VIDEOENHANCE_CLASS, ++ .instance = 2, ++ .mmio_bases = { ++ { .gen = 12, .base = GEN12_VEBOX3_RING_BASE } ++ }, ++ }, ++ [VECS3] = { ++ .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */ ++ .class = VIDEO_ENHANCEMENT_CLASS, ++ .guc_class = GUC_VIDEOENHANCE_CLASS, ++ .instance = 3, ++ .mmio_bases = { ++ { .gen = 12, .base = GEN12_VEBOX4_RING_BASE } ++ }, ++ }, + [CCS0] = { + .hw_id = 0, /* not used in GEN12+, see MI_SEMAPHORE_SIGNAL */ + .class = COMPUTE_CLASS, +@@ -318,6 +372,8 @@ intel_engine_setup(struct drm_i915_private *dev_priv, + + BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH)); + BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH)); ++ BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1)); ++ BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1)); + + if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS)) + return -EINVAL; +diff --git a/drivers/gpu/drm/i915/intel_engine_types.h b/drivers/gpu/drm/i915/intel_engine_types.h +--- a/drivers/gpu/drm/i915/intel_engine_types.h ++++ b/drivers/gpu/drm/i915/intel_engine_types.h +@@ -89,8 +89,8 @@ struct i915_ctx_workarounds { + struct i915_vma *vma; + }; + +-#define I915_MAX_VCS 4 +-#define I915_MAX_VECS 2 ++#define I915_MAX_VCS 8 ++#define I915_MAX_VECS 4 + + /* + * Engine IDs definitions. +@@ -103,11 +103,19 @@ enum intel_engine_id { + VCS1, + VCS2, + VCS3, ++ VCS4, ++ VCS5, ++ VCS6, ++ VCS7, + #define _VCS(n) (VCS0 + (n)) + VECS0, + VECS1, ++ VECS2, ++ VECS3, + #define _VECS(n) (VECS0 + (n)) +- CCS0 ++ CCS0, ++ ++ I915_NUM_ENGINES + }; + + struct st_preempt_hang { +diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h +--- a/drivers/gpu/drm/i915/intel_guc.h ++++ b/drivers/gpu/drm/i915/intel_guc.h +@@ -33,6 +33,7 @@ + #include "intel_guc_log.h" + #include "intel_guc_reg.h" + #include "intel_uc_fw.h" ++#include "intel_engine_types.h" + #include "i915_utils.h" + #include "i915_vma.h" + +diff --git a/drivers/gpu/drm/i915/intel_guc_submission.h b/drivers/gpu/drm/i915/intel_guc_submission.h +--- a/drivers/gpu/drm/i915/intel_guc_submission.h ++++ b/drivers/gpu/drm/i915/intel_guc_submission.h +@@ -27,7 +27,7 @@ + + #include + +-#include "i915_gem.h" ++#include "intel_engine_types.h" + #include "i915_selftest.h" + + struct drm_i915_private; diff --git a/0001-drm-i915-Extra-media-engines-for-ATS-Part-2-interrup.patch b/0001-drm-i915-Extra-media-engines-for-ATS-Part-2-interrup.patch new file mode 100644 index 000000000000..ba449e18fbae --- /dev/null +++ b/0001-drm-i915-Extra-media-engines-for-ATS-Part-2-interrup.patch @@ -0,0 +1,97 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: John Harrison +Date: Fri, 22 Mar 2019 16:26:35 -0700 +Subject: [PATCH] drm/i915: Extra media engines for ATS - Part 2 (interrupts) + +ATS has lots of extra media engines. This patch adds the interrupt +handler support for them. + +v2: Changed debugfs to assume ATS always has VCSx8 + VECSx4 +irrespective of fusings. [Tvrtko Ursulin] + +v3: Changed interrupt masking to check for the presence of each pair +of engines to support fusings [Daniele]. + +Signed-off-by: John Harrison +CC: Tvrtko Ursulin +CC: Daniele Ceraolo Spurio +--- + drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++++++- + drivers/gpu/drm/i915/i915_irq.c | 12 ++++++++++++ + drivers/gpu/drm/i915/i915_reg.h | 3 +++ + 3 files changed, 24 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c +--- a/drivers/gpu/drm/i915/i915_debugfs.c ++++ b/drivers/gpu/drm/i915/i915_debugfs.c +@@ -869,8 +869,17 @@ static int i915_interrupt_info(struct seq_file *m, void *data) + I915_READ(GEN11_VCS0_VCS1_INTR_MASK)); + seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n", + I915_READ(GEN11_VCS2_VCS3_INTR_MASK)); ++ if (IS_ARCTICSOUND(dev_priv)) { ++ seq_printf(m, "VCS4/VCS5 Intr Mask:\t %08x\n", ++ I915_READ(GEN12_VCS4_VCS5_INTR_MASK)); ++ seq_printf(m, "VCS6/VCS7 Intr Mask:\t %08x\n", ++ I915_READ(GEN12_VCS6_VCS7_INTR_MASK)); ++ } + seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n", + I915_READ(GEN11_VECS0_VECS1_INTR_MASK)); ++ if (IS_ARCTICSOUND(dev_priv)) ++ seq_printf(m, "VECS2/VECS3 Intr Mask:\t %08x\n", ++ I915_READ(GEN12_VECS2_VECS3_INTR_MASK)); + seq_printf(m, "GUC/SG Intr Mask:\t %08x\n", + I915_READ(GEN11_GUC_SG_INTR_MASK)); + seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n", +@@ -883,7 +892,6 @@ static int i915_interrupt_info(struct seq_file *m, void *data) + seq_printf(m, "CCS Intr Mask:\t %08x\n", + I915_READ(GEN12_CCS0_RSVD_INTR_MASK)); + } +- + } else if (INTEL_GEN(dev_priv) >= 6) { + for_each_engine(engine, dev_priv, id) { + seq_printf(m, +diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c +--- a/drivers/gpu/drm/i915/i915_irq.c ++++ b/drivers/gpu/drm/i915/i915_irq.c +@@ -3630,7 +3630,13 @@ static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv) + I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~0); + I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~0); + I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~0); ++ if (HAS_ENGINE(dev_priv, VCS4) || HAS_ENGINE(dev_priv, VCS5)) ++ I915_WRITE(GEN12_VCS4_VCS5_INTR_MASK, ~0); ++ if (HAS_ENGINE(dev_priv, VCS6) || HAS_ENGINE(dev_priv, VCS7)) ++ I915_WRITE(GEN12_VCS6_VCS7_INTR_MASK, ~0); + I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~0); ++ if (HAS_ENGINE(dev_priv, VECS2) || (HAS_ENGINE(dev_priv, VECS3)) ++ I915_WRITE(GEN12_VECS2_VECS3_INTR_MASK, ~0); + if (HAS_ENGINE(dev_priv, CCS0)) + I915_WRITE(GEN12_CCS0_RSVD_INTR_MASK, ~0); + +@@ -4289,7 +4295,13 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv) + I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16)); + I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~(irqs | irqs << 16)); + I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs | irqs << 16)); ++ if (HAS_ENGINE(dev_priv, VCS4) || HAS_ENGINE(dev_priv, VCS5)) ++ I915_WRITE(GEN12_VCS4_VCS5_INTR_MASK, ~(irqs | irqs << 16)); ++ if (HAS_ENGINE(dev_priv, VCS6) || HAS_ENGINE(dev_priv, VCS7)) ++ I915_WRITE(GEN12_VCS6_VCS7_INTR_MASK, ~(irqs | irqs << 16)); + I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs | irqs << 16)); ++ if (HAS_ENGINE(dev_priv, VECS2) || HAS_ENGINE(dev_priv, VECS3)) ++ I915_WRITE(GEN12_VECS2_VECS3_INTR_MASK, ~(irqs | irqs << 16)); + if (HAS_ENGINE(dev_priv, CCS0)) + I915_WRITE(GEN12_CCS0_RSVD_INTR_MASK, ~(irqs << 16)); + +diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -7678,7 +7678,10 @@ enum { + #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0) + #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8) + #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac) ++#define GEN12_VCS4_VCS5_INTR_MASK _MMIO(0x1900b0) ++#define GEN12_VCS6_VCS7_INTR_MASK _MMIO(0x1900b4) + #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0) ++#define GEN12_VECS2_VECS3_INTR_MASK _MMIO(0x1900d4) + #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8) + #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec) + #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0) diff --git a/0001-drm-i915-Extra-media-engines-for-ATS-Part-3-reset.patch b/0001-drm-i915-Extra-media-engines-for-ATS-Part-3-reset.patch new file mode 100644 index 000000000000..a4bfed593bd3 --- /dev/null +++ b/0001-drm-i915-Extra-media-engines-for-ATS-Part-3-reset.patch @@ -0,0 +1,54 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: John Harrison +Date: Fri, 22 Mar 2019 16:31:30 -0700 +Subject: [PATCH] drm/i915: Extra media engines for ATS - Part 3 (reset) + +ATS has lots of extra media engines. This patch adds the reset support +for them. + +Signed-off-by: John Harrison +--- + drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ + drivers/gpu/drm/i915/i915_reset.c | 6 ++++++ + 2 files changed, 14 insertions(+) + +diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -416,10 +416,18 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) + #define GEN11_GRDOM_MEDIA2 (1 << 6) + #define GEN11_GRDOM_MEDIA3 (1 << 7) + #define GEN11_GRDOM_MEDIA4 (1 << 8) ++#define GEN11_GRDOM_MEDIA5 (1 << 9) ++#define GEN11_GRDOM_MEDIA6 (1 << 10) ++#define GEN11_GRDOM_MEDIA7 (1 << 11) ++#define GEN11_GRDOM_MEDIA8 (1 << 12) + #define GEN11_GRDOM_VECS (1 << 13) + #define GEN11_GRDOM_VECS2 (1 << 14) ++#define GEN11_GRDOM_VECS3 (1 << 15) ++#define GEN11_GRDOM_VECS4 (1 << 16) + #define GEN11_GRDOM_SFC0 (1 << 17) + #define GEN11_GRDOM_SFC1 (1 << 18) ++#define GEN11_GRDOM_SFC2 (1 << 19) ++#define GEN11_GRDOM_SFC3 (1 << 20) + + #define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1)) + #define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance)) +diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c +--- a/drivers/gpu/drm/i915/i915_reset.c ++++ b/drivers/gpu/drm/i915/i915_reset.c +@@ -439,8 +439,14 @@ static int gen11_reset_engines(struct drm_i915_private *i915, + [VCS1] = GEN11_GRDOM_MEDIA2, + [VCS2] = GEN11_GRDOM_MEDIA3, + [VCS3] = GEN11_GRDOM_MEDIA4, ++ [VCS4] = GEN11_GRDOM_MEDIA5, ++ [VCS5] = GEN11_GRDOM_MEDIA6, ++ [VCS6] = GEN11_GRDOM_MEDIA7, ++ [VCS7] = GEN11_GRDOM_MEDIA8, + [VECS0] = GEN11_GRDOM_VECS, + [VECS1] = GEN11_GRDOM_VECS2, ++ [VECS2] = GEN11_GRDOM_VECS3, ++ [VECS3] = GEN11_GRDOM_VECS4, + [CCS0] = GEN11_GRDOM_RENDER, /* FIXME: RCS/CCS engine reset won't be as simple */ + }; + struct intel_engine_cs *engine; diff --git a/0001-drm-i915-Extra-media-engines-for-ATS-Part-4-FW.patch b/0001-drm-i915-Extra-media-engines-for-ATS-Part-4-FW.patch new file mode 100644 index 000000000000..d19ee8d326d6 --- /dev/null +++ b/0001-drm-i915-Extra-media-engines-for-ATS-Part-4-FW.patch @@ -0,0 +1,110 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: John Harrison +Date: Fri, 22 Mar 2019 17:10:55 -0700 +Subject: [PATCH] drm/i915: Extra media engines for ATS - Part 4 (FW) + +ATS has lots of extra media engines. This patch adds the forcewake +support for them. + +Signed-off-by: John Harrison +--- + drivers/gpu/drm/i915/intel_uncore.c | 28 +++++++++++++++++++++++++++- + drivers/gpu/drm/i915/intel_uncore.h | 12 ++++++++++++ + 2 files changed, 39 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c +--- a/drivers/gpu/drm/i915/intel_uncore.c ++++ b/drivers/gpu/drm/i915/intel_uncore.c +@@ -41,8 +41,14 @@ static const char * const forcewake_domain_names[] = { + "vdbox1", + "vdbox2", + "vdbox3", ++ "vdbox4", ++ "vdbox5", ++ "vdbox6", ++ "vdbox7", + "vebox0", + "vebox1", ++ "vebox2", ++ "vebox3", + }; + + const char * +@@ -930,6 +936,12 @@ static const i915_reg_t gen12_shadowed_regs[] = { + RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */ + RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */ + RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */ ++ RING_TAIL(GEN12_BSD5_RING_BASE), /* 0x1E0000 (base) */ ++ RING_TAIL(GEN12_BSD6_RING_BASE), /* 0x1E4000 (base) */ ++ RING_TAIL(GEN12_VEBOX3_RING_BASE), /* 0x1E8000 (base) */ ++ RING_TAIL(GEN12_BSD7_RING_BASE), /* 0x1F0000 (base) */ ++ RING_TAIL(GEN12_BSD8_RING_BASE), /* 0x1F4000 (base) */ ++ RING_TAIL(GEN12_VEBOX4_RING_BASE), /* 0x1F8000 (base) */ + /* TODO: Other registers are not yet used */ + }; + +@@ -1119,7 +1131,15 @@ static const struct intel_forcewake_range __gen12_fw_ranges[] = { + GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER), + GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), + GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), +- GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1) ++ GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1), ++ GEN_FW_RANGE(0x1dc000, 0x1dffff, FORCEWAKE_BLITTER), ++ GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), ++ GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), ++ GEN_FW_RANGE(0x1e8000, 0x1ebfff, FORCEWAKE_MEDIA_VEBOX2), ++ GEN_FW_RANGE(0x1ec000, 0x1effff, FORCEWAKE_BLITTER), ++ GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), ++ GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), ++ GEN_FW_RANGE(0x1f8000, 0x1fbfff, FORCEWAKE_MEDIA_VEBOX3), + }; + + static void +@@ -1417,8 +1437,14 @@ static void fw_domain_init(struct intel_uncore *uncore, + BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1)); + BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2)); + BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3)); ++ BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX4 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX4)); ++ BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX5 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX5)); ++ BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX6 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX6)); ++ BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX7 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX7)); + BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0)); + BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1)); ++ BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX2)); ++ BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX3)); + + + d->mask = BIT(domain_id); +diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h +--- a/drivers/gpu/drm/i915/intel_uncore.h ++++ b/drivers/gpu/drm/i915/intel_uncore.h +@@ -44,8 +44,14 @@ enum forcewake_domain_id { + FW_DOMAIN_ID_MEDIA_VDBOX1, + FW_DOMAIN_ID_MEDIA_VDBOX2, + FW_DOMAIN_ID_MEDIA_VDBOX3, ++ FW_DOMAIN_ID_MEDIA_VDBOX4, ++ FW_DOMAIN_ID_MEDIA_VDBOX5, ++ FW_DOMAIN_ID_MEDIA_VDBOX6, ++ FW_DOMAIN_ID_MEDIA_VDBOX7, + FW_DOMAIN_ID_MEDIA_VEBOX0, + FW_DOMAIN_ID_MEDIA_VEBOX1, ++ FW_DOMAIN_ID_MEDIA_VEBOX2, ++ FW_DOMAIN_ID_MEDIA_VEBOX3, + + FW_DOMAIN_ID_COUNT + }; +@@ -58,8 +64,14 @@ enum forcewake_domains { + FORCEWAKE_MEDIA_VDBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX1), + FORCEWAKE_MEDIA_VDBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX2), + FORCEWAKE_MEDIA_VDBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX3), ++ FORCEWAKE_MEDIA_VDBOX4 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX4), ++ FORCEWAKE_MEDIA_VDBOX5 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX5), ++ FORCEWAKE_MEDIA_VDBOX6 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX6), ++ FORCEWAKE_MEDIA_VDBOX7 = BIT(FW_DOMAIN_ID_MEDIA_VDBOX7), + FORCEWAKE_MEDIA_VEBOX0 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX0), + FORCEWAKE_MEDIA_VEBOX1 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX1), ++ FORCEWAKE_MEDIA_VEBOX2 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX2), ++ FORCEWAKE_MEDIA_VEBOX3 = BIT(FW_DOMAIN_ID_MEDIA_VEBOX3), + + FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1 + }; diff --git a/0001-drm-i915-Extra-media-engines-for-ATS-Part-5-UAPI.patch b/0001-drm-i915-Extra-media-engines-for-ATS-Part-5-UAPI.patch new file mode 100644 index 000000000000..275437f27a23 --- /dev/null +++ b/0001-drm-i915-Extra-media-engines-for-ATS-Part-5-UAPI.patch @@ -0,0 +1,30 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: John Harrison +Date: Fri, 22 Mar 2019 17:12:56 -0700 +Subject: [PATCH] drm/i915: Extra media engines for ATS - Part 5 (UAPI) + +ATS has lots of extra media engines. This patch enables them in the +engine query UAPI so that they can actually be used. + +Signed-off-by: John Harrison +--- + drivers/gpu/drm/i915/i915_pci.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c +--- a/drivers/gpu/drm/i915/i915_pci.c ++++ b/drivers/gpu/drm/i915/i915_pci.c +@@ -780,8 +780,11 @@ static const struct intel_device_info intel_arcticsound_info = { + .is_alpha_support = 1, + .has_guc_dist_db = 0, + .engine_mask = +- BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VECS1) | BIT(VCS0) | +- BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | BIT(CCS0), ++ BIT(RCS0) | BIT(BCS0) | ++ BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | ++ BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | ++ BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) | ++ BIT(CCS0), + }; + + #undef GEN diff --git a/0001-drm-i915-ats-ATS-has-MMIO-doorbells.patch b/0001-drm-i915-ats-ATS-has-MMIO-doorbells.patch index 1b216a7ea5b4..902179ce484d 100644 --- a/0001-drm-i915-ats-ATS-has-MMIO-doorbells.patch +++ b/0001-drm-i915-ats-ATS-has-MMIO-doorbells.patch @@ -21,5 +21,5 @@ diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c .has_guc_dist_db = 0, + .has_guc_mmio_db = 1, .engine_mask = - BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VECS1) | BIT(VCS0) | - BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | BIT(CCS0), + BIT(RCS0) | BIT(BCS0) | + BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) | diff --git a/0001-drm-i915-ats-Disable-all-display-device-information-.patch b/0001-drm-i915-ats-Disable-all-display-device-information-.patch index fa5435a374fe..15358a1e4ef0 100644 --- a/0001-drm-i915-ats-Disable-all-display-device-information-.patch +++ b/0001-drm-i915-ats-Disable-all-display-device-information-.patch @@ -19,10 +19,10 @@ Acked-by: Lucas De Marchi diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c -@@ -818,6 +818,7 @@ static const struct intel_device_info intel_arcticsound_info = { - .engine_mask = - BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VECS1) | BIT(VCS0) | - BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | BIT(CCS0), +@@ -821,6 +821,7 @@ static const struct intel_device_info intel_arcticsound_info = { + BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) | + BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) | + BIT(CCS0), + .display = { 0 }, }; diff --git a/0001-drm-i915-guc-Support-for-VFPF-relay-messages.patch b/0001-drm-i915-guc-Support-for-VFPF-relay-messages.patch index 0873dd1ef112..8b2163a221db 100644 --- a/0001-drm-i915-guc-Support-for-VFPF-relay-messages.patch +++ b/0001-drm-i915-guc-Support-for-VFPF-relay-messages.patch @@ -59,9 +59,9 @@ diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h #include "intel_guc_reg.h" +#include "intel_guc_relay.h" #include "intel_uc_fw.h" + #include "intel_engine_types.h" #include "i915_utils.h" - #include "i915_vma.h" -@@ -50,6 +51,7 @@ struct intel_guc { +@@ -51,6 +52,7 @@ struct intel_guc { struct intel_uc_fw fw; struct intel_guc_log log; struct intel_guc_ct ct; diff --git a/0001-drm-i915-selftests-Allow-for-larger-engine-counts.patch b/0001-drm-i915-selftests-Allow-for-larger-engine-counts.patch new file mode 100644 index 000000000000..dd97c611fc41 --- /dev/null +++ b/0001-drm-i915-selftests-Allow-for-larger-engine-counts.patch @@ -0,0 +1,85 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: John Harrison +Date: Fri, 22 Mar 2019 16:47:30 -0700 +Subject: [PATCH] drm/i915/selftests: Allow for larger engine counts + +Increasing the engine count causes a couple of local array variables +to exceed the kernel stack limit. So make them dynamic allocations +instead. + +Signed-off-by: John Harrison +--- + drivers/gpu/drm/i915/selftests/i915_request.c | 7 ++++++- + drivers/gpu/drm/i915/selftests/intel_lrc.c | 10 ++++++++-- + 2 files changed, 14 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c +--- a/drivers/gpu/drm/i915/selftests/i915_request.c ++++ b/drivers/gpu/drm/i915/selftests/i915_request.c +@@ -1097,7 +1097,7 @@ max_batches(struct i915_gem_context *ctx, struct intel_engine_cs *engine) + static int live_breadcrumbs_smoketest(void *arg) + { + struct drm_i915_private *i915 = arg; +- struct smoketest t[I915_NUM_ENGINES]; ++ struct smoketest *t; + unsigned int ncpus = num_online_cpus(); + unsigned long num_waits, num_fences; + struct intel_engine_cs *engine; +@@ -1117,6 +1117,10 @@ static int live_breadcrumbs_smoketest(void *arg) + * On real hardware this time. + */ + ++ t = kmalloc_array(I915_NUM_ENGINES, sizeof(*t), GFP_KERNEL); ++ if (!t) ++ return -ENOMEM; ++ + wakeref = intel_runtime_pm_get(i915); + + file = mock_file(i915); +@@ -1226,6 +1230,7 @@ static int live_breadcrumbs_smoketest(void *arg) + out_rpm: + intel_runtime_pm_put(i915, wakeref); + ++ kfree(t); + return ret; + } + +diff --git a/drivers/gpu/drm/i915/selftests/intel_lrc.c b/drivers/gpu/drm/i915/selftests/intel_lrc.c +--- a/drivers/gpu/drm/i915/selftests/intel_lrc.c ++++ b/drivers/gpu/drm/i915/selftests/intel_lrc.c +@@ -964,12 +964,16 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags) + #define BATCH BIT(0) + { + struct task_struct *tsk[I915_NUM_ENGINES] = {}; +- struct preempt_smoke arg[I915_NUM_ENGINES]; ++ struct preempt_smoke *arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + unsigned long count; + int err = 0; + ++ arg = kmalloc_array(I915_NUM_ENGINES, sizeof(*arg), GFP_KERNEL); ++ if (!arg) ++ return -ENOMEM; ++ + mutex_unlock(&smoke->i915->drm.struct_mutex); + + for_each_engine(engine, smoke->i915, id) { +@@ -979,7 +983,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags) + arg[id].batch = NULL; + arg[id].count = 0; + +- tsk[id] = kthread_run(smoke_crescendo_thread, &arg, ++ tsk[id] = kthread_run(smoke_crescendo_thread, arg, + "igt/smoke:%d", id); + if (IS_ERR(tsk[id])) { + err = PTR_ERR(tsk[id]); +@@ -1009,6 +1013,8 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags) + pr_info("Submitted %lu crescendo:%x requests across %d engines and %d contexts\n", + count, flags, + RUNTIME_INFO(smoke->i915)->num_engines, smoke->ncontext); ++ ++ kfree(arg); + return 0; + } +