@@ -869,8 +869,17 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
+ if (IS_ARCTICSOUND(dev_priv)) {
+ seq_printf(m, "VCS4/VCS5 Intr Mask:\t %08x\n",
+ I915_READ(GEN12_VCS4_VCS5_INTR_MASK));
+ seq_printf(m, "VCS6/VCS7 Intr Mask:\t %08x\n",
+ I915_READ(GEN12_VCS6_VCS7_INTR_MASK));
+ }
seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
+ if (IS_ARCTICSOUND(dev_priv))
+ seq_printf(m, "VECS2/VECS3 Intr Mask:\t %08x\n",
+ I915_READ(GEN12_VECS2_VECS3_INTR_MASK));
seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
I915_READ(GEN11_GUC_SG_INTR_MASK));
seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
@@ -883,7 +892,6 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
seq_printf(m, "CCS Intr Mask:\t %08x\n",
I915_READ(GEN12_CCS0_RSVD_INTR_MASK));
}
-
} else if (INTEL_GEN(dev_priv) >= 6) {
for_each_engine(engine, dev_priv, id) {
seq_printf(m,
@@ -3630,7 +3630,13 @@ static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~0);
I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~0);
I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~0);
+ if (HAS_ENGINE(dev_priv, VCS4) || HAS_ENGINE(dev_priv, VCS5))
+ I915_WRITE(GEN12_VCS4_VCS5_INTR_MASK, ~0);
+ if (HAS_ENGINE(dev_priv, VCS6) || HAS_ENGINE(dev_priv, VCS7))
+ I915_WRITE(GEN12_VCS6_VCS7_INTR_MASK, ~0);
I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~0);
+ if (HAS_ENGINE(dev_priv, VECS2) || (HAS_ENGINE(dev_priv, VECS3))
+ I915_WRITE(GEN12_VECS2_VECS3_INTR_MASK, ~0);
if (HAS_ENGINE(dev_priv, CCS0))
I915_WRITE(GEN12_CCS0_RSVD_INTR_MASK, ~0);
@@ -4289,7 +4295,13 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16));
I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~(irqs | irqs << 16));
I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs | irqs << 16));
+ if (HAS_ENGINE(dev_priv, VCS4) || HAS_ENGINE(dev_priv, VCS5))
+ I915_WRITE(GEN12_VCS4_VCS5_INTR_MASK, ~(irqs | irqs << 16));
+ if (HAS_ENGINE(dev_priv, VCS6) || HAS_ENGINE(dev_priv, VCS7))
+ I915_WRITE(GEN12_VCS6_VCS7_INTR_MASK, ~(irqs | irqs << 16));
I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs | irqs << 16));
+ if (HAS_ENGINE(dev_priv, VECS2) || HAS_ENGINE(dev_priv, VECS3))
+ I915_WRITE(GEN12_VECS2_VECS3_INTR_MASK, ~(irqs | irqs << 16));
if (HAS_ENGINE(dev_priv, CCS0))
I915_WRITE(GEN12_CCS0_RSVD_INTR_MASK, ~(irqs << 16));
@@ -7678,7 +7678,10 @@ enum {
#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
#define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
#define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
+#define GEN12_VCS4_VCS5_INTR_MASK _MMIO(0x1900b0)
+#define GEN12_VCS6_VCS7_INTR_MASK _MMIO(0x1900b4)
#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
+#define GEN12_VECS2_VECS3_INTR_MASK _MMIO(0x1900d4)
#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)