| Message ID | 20190403233539.31828-4-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment | expand |
On Wed, Apr 03, 2019 at 04:35:36PM -0700, José Roberto de Souza wrote: > This interlaced restriction applies to all gens, not only to Haswell. I believe this came from VLV times and I doubt we would be impacted by it ever, but better to protect just in case: Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/intel_psr.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index a84da931c3be..bb97c1657493 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -627,8 +627,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, > return; > } > > - if (IS_HASWELL(dev_priv) && > - adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { > + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { > DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); > return; > } > -- > 2.21.0 >
On Wed, 2019-04-03 at 17:29 -0700, Rodrigo Vivi wrote: > On Wed, Apr 03, 2019 at 04:35:36PM -0700, José Roberto de Souza wrote: > > This interlaced restriction applies to all gens, not only to Haswell. > > I believe this came from VLV times and I doubt we would be > impacted by it ever, but better to protect just in case: > > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > --- > > drivers/gpu/drm/i915/intel_psr.c | 3 +-- > > 1 file changed, 1 insertion(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index a84da931c3be..bb97c1657493 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -627,8 +627,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, > > return; > > } > > > > - if (IS_HASWELL(dev_priv) && > > - adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { > > + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { > > DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); It'd be nice to change this to "interlaced mode" Noticed that the spec says PSR does not work with Stereo 3d mode as well. But, that should be okay since we don't set stereo_allowed for DP. Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > return; > > } > > -- > > 2.21.0 > >
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index a84da931c3be..bb97c1657493 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -627,8 +627,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, return; } - if (IS_HASWELL(dev_priv) && - adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); return; }
This interlaced restriction applies to all gens, not only to Haswell. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/intel_psr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)