From patchwork Thu Apr 4 13:47:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pu Wen X-Patchwork-Id: 10885643 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 760B8139A for ; Thu, 4 Apr 2019 13:52:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5FB6428640 for ; Thu, 4 Apr 2019 13:52:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 53E3A28722; Thu, 4 Apr 2019 13:52:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E736828640 for ; Thu, 4 Apr 2019 13:52:27 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hC2lJ-00084p-Qb; Thu, 04 Apr 2019 13:50:37 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hC2lJ-00084T-3r for xen-devel@lists.xenproject.org; Thu, 04 Apr 2019 13:50:37 +0000 X-Inumbo-ID: 9db15a2e-56e0-11e9-92d7-bc764e045a96 Received: from spam2.hygon.cn (unknown [110.188.70.11]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 9db15a2e-56e0-11e9-92d7-bc764e045a96; Thu, 04 Apr 2019 13:50:35 +0000 (UTC) Received: from MK-DB.hygon.cn ([172.23.18.60]) by spam2.hygon.cn with ESMTP id x34DlU4H079678; Thu, 4 Apr 2019 21:47:30 +0800 (GMT-8) (envelope-from puwen@hygon.cn) Received: from cncheex01.Hygon.cn ([172.23.18.10]) by MK-DB.hygon.cn with ESMTP id x34DlQl9042421; Thu, 4 Apr 2019 21:47:26 +0800 (GMT-8) (envelope-from puwen@hygon.cn) Received: from pw-vbox.hygon.cn (172.23.18.44) by cncheex01.Hygon.cn (172.23.18.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1466.3; Thu, 4 Apr 2019 21:47:26 +0800 From: Pu Wen To: Date: Thu, 4 Apr 2019 21:47:16 +0800 Message-ID: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [172.23.18.44] X-ClientProxiedBy: cncheex02.Hygon.cn (172.23.18.12) To cncheex01.Hygon.cn (172.23.18.10) X-MAIL: spam2.hygon.cn x34DlU4H079678 X-DNSRBL: Subject: [Xen-devel] [PATCH v5 10/15] x86/pv: Add Hygon Dhyana support to emulate MSRs access X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Pu Wen , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Jan Beulich , Andrew Cooper Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and counter MSRs, hardware configuration MSR, MMIO configuration base address MSR, MPERF/APERF MSRs) as AMD CPU does, so add Hygon Dhyana support to the PV emulation infrastructure by using the code path of AMD. Signed-off-by: Pu Wen Acked-by: Jan Beulich --- xen/arch/x86/pv/emul-priv-op.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 84ce67c..4f73375 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -924,7 +924,9 @@ static int read_msr(unsigned int reg, uint64_t *val, /* fall through */ case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5: case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3: - if ( vpmu_msr || (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) ) + if ( vpmu_msr || + (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) || + (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) ) { if ( vpmu_do_rdmsr(reg, val) ) break; @@ -1006,7 +1008,8 @@ static int write_msr(unsigned int reg, uint64_t val, case MSR_K8_PSTATE6: case MSR_K8_PSTATE7: case MSR_K8_HWCR: - if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ) + if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD && + boot_cpu_data.x86_vendor != X86_VENDOR_HYGON ) break; if ( likely(!is_cpufreq_controller(currd)) || wrmsr_safe(reg, val) == 0 ) @@ -1027,8 +1030,9 @@ static int write_msr(unsigned int reg, uint64_t val, break; case MSR_FAM10H_MMIO_CONF_BASE: - if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD || - boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 ) + if ( (boot_cpu_data.x86_vendor != X86_VENDOR_AMD || + boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17) && + boot_cpu_data.x86_vendor != X86_VENDOR_HYGON ) break; if ( !is_hwdom_pinned_vcpu(curr) ) return X86EMUL_OKAY; @@ -1067,7 +1071,8 @@ static int write_msr(unsigned int reg, uint64_t val, case MSR_IA32_MPERF: case MSR_IA32_APERF: if ( (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) && - (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) ) + (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) && + (boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) ) break; if ( likely(!is_cpufreq_controller(currd)) || wrmsr_safe(reg, val) == 0 ) @@ -1099,7 +1104,9 @@ static int write_msr(unsigned int reg, uint64_t val, vpmu_msr = true; case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5: case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3: - if ( vpmu_msr || (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) ) + if ( vpmu_msr || + (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) || + (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) ) { if ( (vpmu_mode & XENPMU_MODE_ALL) && !is_hardware_domain(currd) )