[v5,13/15] x86/traps: Add Hygon Dhyana support
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Message ID 1c0782f1c136679f460960924ccb69d3c6b84a82.1554382869.git.puwen@hygon.cn
State New, archived
Headers show
  • Add support for Hygon Dhyana Family 18h processor
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Commit Message

Pu Wen April 4, 2019, 1:47 p.m. UTC
The Hygon Dhyana processor has the methold to get the last exception
source IP from MSR0000_01DD. So add support for it if the boot param
ler is true.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
 xen/arch/x86/traps.c | 3 +++
 1 file changed, 3 insertions(+)

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diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 05ddc39..97bf9e2 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -1973,6 +1973,9 @@  static unsigned int calc_ler_msr(void)
             return MSR_IA32_LASTINTFROMIP;
+    case X86_VENDOR_HYGON:
+        return MSR_IA32_LASTINTFROMIP;
     return 0;