[RFC,v2,5/5] mips: ralink: mt7620: add nodes for clocks

Commit Message

NOGUCHI Hiroshi April 5, 2019, 12:01 a.m. UTC

Signed-off-by: NOGUCHI Hiroshi <[e-mail]>
---
 arch/mips/boot/dts/ralink/mt7620a.dtsi | 46 ++++++++++++++++++++++++--
 1 file changed, 43 insertions(+), 3 deletions(-)

Patch

diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi
index 1f6e5320f486..7c98cb6bb5b9 100644
--- a/arch/mips/boot/dts/ralink/mt7620a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
@@ -1,15 +1,27 @@ 
 // SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mt7620-clk.h>
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
 	compatible = "ralink,mtk7620a-soc";
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
 			compatible = "mips,mips24KEc";
+			device_type = "cpu";
+			reg = <0>;
 		};
 	};
 
+	resetc: reset-controller {
+		compatible = "ralink,rt2880-reset";
+		#reset-cells = <1>;
+	};
+
 	cpuintc: cpuintc {
 		#address-cells = <0>;
 		#interrupt-cells = <1>;
@@ -17,6 +29,28 @@ 
 		compatible = "mti,cpu-interrupt-controller";
 	};
 
+	pll: pll {
+		compatible = "mediatek,mt7620-pll";
+		#clock-cells = <1>;
+		clock-output-names = "cpu", "sys", "periph", "pcmi2s", "xtal";
+	};
+
+	clkctrl: clkctrl {
+		compatible = "ralink,rt2880-clock";
+		#clock-cells = <1>;
+		ralink,sysctl = <&sysc>;
+
+		clock-indices =
+				<12>,
+				<16>, <17>, <18>, <19>;
+		clock-output-names =
+				"uart",
+				"i2c", "i2s", "spi", "uartl";
+		clocks =
+				<&pll MT7620_CLK_PERIPH>,
+				<&pll MT7620_CLK_PERIPH>, <&pll MT7620_CLK_PCMI2S>, <&pll MT7620_CLK_SYS>, <&pll MT7620_CLK_PERIPH>;
+	};
+
 	palmbus@10000000 {
 		compatible = "palmbus";
 		reg = <0x10000000 0x200000>;
@@ -25,8 +59,8 @@ 
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		sysc@0 {
-			compatible = "ralink,mt7620a-sysc";
+		sysc: sysc@0 {
+			compatible = "ralink,mt7620a-sysc", "syscon";
 			reg = <0x0 0x100>;
 		};
 
@@ -46,10 +80,16 @@ 
 			reg = <0x300 0x100>;
 		};
 
-		uartlite@c00 {
+		uartlite: uartlite@c00 {
 			compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
 			reg = <0xc00 0x100>;
 
+			clocks = <&clkctrl 19>;
+			clock-names = "uartl";
+
+			resets = <&resetc 19>;
+			reset-names = "uartl";
+
 			interrupt-parent = <&intc>;
 			interrupts = <12>;