[V2,06/20] spi: tegra114: set supported bits per word
diff mbox series

Message ID 1554423259-26056-6-git-send-email-skomatineni@nvidia.com
State Accepted
Commit f0a0bc90c6e7060778911c2b55d085105809d6cf
Headers show
Series
  • [V2,01/20] spi: tegra114: fix PIO transfer
Related show

Commit Message

Sowjanya Komatineni April 5, 2019, 12:14 a.m. UTC
Tegra SPI supports 4 through 32 bits per word.

This patch sets bits_per_word_mask accordingly to support transfer
with these bits per word.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/spi/spi-tegra114.c | 1 +
 1 file changed, 1 insertion(+)

Patch
diff mbox series

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index e0f20fad5df2..191233eae149 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -1153,6 +1153,7 @@  static int tegra_spi_probe(struct platform_device *pdev)
 
 	/* the spi->mode bits understood by this driver: */
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
+	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
 	master->setup = tegra_spi_setup;
 	master->transfer_one_message = tegra_spi_transfer_one_message;
 	master->num_chipselect = MAX_CHIP_SELECT;