[2/2] dt-bindings: cpufreq: Document operating-points-v2-sunxi-cpu
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Message ID 20190405102455.15311-3-tiny.windzz@gmail.com
State New
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  • cpufreq: Add sunxi nvmem based CPU scaling driver
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Commit Message

Frank Lee April 5, 2019, 10:24 a.m. UTC
Allwinner Process Voltage Scaling Tables defines the voltage and
frequency value  based on the speedbin blown in the efuse combination.
The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to
provide the OPP framework with required information.
This is used to determine the voltage and frequency value for each
OPP of operating-points-v2 table when it is parsed by the OPP framework.

This change adds documentation for the DT bindings.
The "operating-points-v2-sunxi-cpu" DT extends the "operating-points-v2"
with following parameters:
- nvmem-cells (NVMEM area containig the speedbin information)
- opp-supported-hw: A single 32 bit bitmap value,
  representing compatible HW:
			0:      speedbin 0
			1:      speedbin 1
			2:      speedbin 2
			3-31:   unused

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
---
 .../bindings/opp/sunxi-nvmem-cpufreq.txt      | 235 ++++++++++++++++++
 1 file changed, 235 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt

Comments

Maxime Ripard April 5, 2019, 2:55 p.m. UTC | #1
Hi,

On Fri, Apr 05, 2019 at 06:24:55AM -0400, Yangtao Li wrote:
> Allwinner Process Voltage Scaling Tables defines the voltage and
> frequency value  based on the speedbin blown in the efuse combination.
> The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to
> provide the OPP framework with required information.
> This is used to determine the voltage and frequency value for each
> OPP of operating-points-v2 table when it is parsed by the OPP framework.
>
> This change adds documentation for the DT bindings.
> The "operating-points-v2-sunxi-cpu" DT extends the "operating-points-v2"
> with following parameters:
> - nvmem-cells (NVMEM area containig the speedbin information)
> - opp-supported-hw: A single 32 bit bitmap value,
>   representing compatible HW:
> 			0:      speedbin 0
> 			1:      speedbin 1
> 			2:      speedbin 2
> 			3-31:   unused
>
> Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
> ---
>  .../bindings/opp/sunxi-nvmem-cpufreq.txt      | 235 ++++++++++++++++++
>  1 file changed, 235 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
>
> diff --git a/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
> new file mode 100644
> index 000000000000..80201d4e5147
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
> @@ -0,0 +1,235 @@
> +Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings
> +===================================
> +
> +For some SoCs, the CPU frequency subset and voltage value of each OPP
> +varies based on the silicon variant in use. Allwinner Process Voltage
> +Scaling Tables defines the voltage and frequency value  based on the
> +speedbin blown in the efuse combination. The sunxi-cpufreq-nvmem driver
> +reads the efuse value from the SoC to provide the OPP framework with
> +required information.
> +
> +Required properties:
> +--------------------
> +In 'cpus' nodes:
> +- operating-points-v2: Phandle to the operating-points-v2 table to use.
> +
> +In 'operating-points-v2' table:
> +- compatible: Should be
> +	- 'operating-points-v2-sunxi-cpu'.
> +- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
> +		efuse registers that has information about the
> +		speedbin that is used to select the right frequency/voltage
> +		value pair.
> +		Please refer the for nvmem-cells
> +		bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
> +		and also examples below.
> +
> +In every OPP node:
> +- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
> +		    Bitmap:
> +			0:	speedbin 0
> +			1:	speedbin 1
> +			2:	speedbin 2
> +			3-31:	unused

I'm wondering if that's the right approach.

I guess we could also have three different OPP tables, and pass them
all three through a phandle array, and have the kernel code select
which one is relevant based on the SID content

Another option would be to use the OF_DYNAMIC code to fill
operating-points-v2 at kernel boot, before (or when) cpufreq kicks in.

ATF could also do that work.

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Samuel Holland April 6, 2019, 3:26 a.m. UTC | #2
On 4/5/19 9:55 AM, Maxime Ripard wrote:
> Hi,
> 
> On Fri, Apr 05, 2019 at 06:24:55AM -0400, Yangtao Li wrote:
>> Allwinner Process Voltage Scaling Tables defines the voltage and
>> frequency value  based on the speedbin blown in the efuse combination.
>> The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to
>> provide the OPP framework with required information.
>> This is used to determine the voltage and frequency value for each
>> OPP of operating-points-v2 table when it is parsed by the OPP framework.
>>
>> This change adds documentation for the DT bindings.
>> The "operating-points-v2-sunxi-cpu" DT extends the "operating-points-v2"
>> with following parameters:
>> - nvmem-cells (NVMEM area containig the speedbin information)
>> - opp-supported-hw: A single 32 bit bitmap value,
>>   representing compatible HW:
>> 			0:      speedbin 0
>> 			1:      speedbin 1
>> 			2:      speedbin 2
>> 			3-31:   unused
>>
>> Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
>> ---
>>  .../bindings/opp/sunxi-nvmem-cpufreq.txt      | 235 ++++++++++++++++++
>>  1 file changed, 235 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
>>
>> diff --git a/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
>> new file mode 100644
>> index 000000000000..80201d4e5147
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
>> @@ -0,0 +1,235 @@
>> +Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings
>> +===================================
>> +
>> +For some SoCs, the CPU frequency subset and voltage value of each OPP
>> +varies based on the silicon variant in use. Allwinner Process Voltage
>> +Scaling Tables defines the voltage and frequency value  based on the
>> +speedbin blown in the efuse combination. The sunxi-cpufreq-nvmem driver
>> +reads the efuse value from the SoC to provide the OPP framework with
>> +required information.
>> +
>> +Required properties:
>> +--------------------
>> +In 'cpus' nodes:
>> +- operating-points-v2: Phandle to the operating-points-v2 table to use.
>> +
>> +In 'operating-points-v2' table:
>> +- compatible: Should be
>> +	- 'operating-points-v2-sunxi-cpu'.
>> +- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
>> +		efuse registers that has information about the
>> +		speedbin that is used to select the right frequency/voltage
>> +		value pair.
>> +		Please refer the for nvmem-cells
>> +		bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
>> +		and also examples below.
>> +
>> +In every OPP node:
>> +- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
>> +		    Bitmap:
>> +			0:	speedbin 0
>> +			1:	speedbin 1
>> +			2:	speedbin 2
>> +			3-31:	unused
> 
> I'm wondering if that's the right approach.
> 
> I guess we could also have three different OPP tables, and pass them
> all three through a phandle array, and have the kernel code select
> which one is relevant based on the SID content
> 
> Another option would be to use the OF_DYNAMIC code to fill
> operating-points-v2 at kernel boot, before (or when) cpufreq kicks in.
> 
> ATF could also do that work.

While ATF has code to read and parse the DTB (which it uses to set up the PMIC),
it's not really in a position to modify the DTB. For one thing, it only has
access to the DTB appended to u-boot, not any DTB loaded from disk. And for two,
that would add a significant amount of code, when ATF is already reaching its
size limits.

Cheers,
Samuel
Frank Lee April 8, 2019, 4:13 p.m. UTC | #3
On Fri, Apr 5, 2019 at 10:55 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> Hi,
>
> On Fri, Apr 05, 2019 at 06:24:55AM -0400, Yangtao Li wrote:
> > Allwinner Process Voltage Scaling Tables defines the voltage and
> > frequency value  based on the speedbin blown in the efuse combination.
> > The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to
> > provide the OPP framework with required information.
> > This is used to determine the voltage and frequency value for each
> > OPP of operating-points-v2 table when it is parsed by the OPP framework.
> >
> > This change adds documentation for the DT bindings.
> > The "operating-points-v2-sunxi-cpu" DT extends the "operating-points-v2"
> > with following parameters:
> > - nvmem-cells (NVMEM area containig the speedbin information)
> > - opp-supported-hw: A single 32 bit bitmap value,
> >   representing compatible HW:
> >                       0:      speedbin 0
> >                       1:      speedbin 1
> >                       2:      speedbin 2
> >                       3-31:   unused
> >
> > Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
> > ---
> >  .../bindings/opp/sunxi-nvmem-cpufreq.txt      | 235 ++++++++++++++++++
> >  1 file changed, 235 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
> >
> > diff --git a/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
> > new file mode 100644
> > index 000000000000..80201d4e5147
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
> > @@ -0,0 +1,235 @@
> > +Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings
> > +===================================
> > +
> > +For some SoCs, the CPU frequency subset and voltage value of each OPP
> > +varies based on the silicon variant in use. Allwinner Process Voltage
> > +Scaling Tables defines the voltage and frequency value  based on the
> > +speedbin blown in the efuse combination. The sunxi-cpufreq-nvmem driver
> > +reads the efuse value from the SoC to provide the OPP framework with
> > +required information.
> > +
> > +Required properties:
> > +--------------------
> > +In 'cpus' nodes:
> > +- operating-points-v2: Phandle to the operating-points-v2 table to use.
> > +
> > +In 'operating-points-v2' table:
> > +- compatible: Should be
> > +     - 'operating-points-v2-sunxi-cpu'.
> > +- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
> > +             efuse registers that has information about the
> > +             speedbin that is used to select the right frequency/voltage
> > +             value pair.
> > +             Please refer the for nvmem-cells
> > +             bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
> > +             and also examples below.
> > +
> > +In every OPP node:
> > +- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
> > +                 Bitmap:
> > +                     0:      speedbin 0
> > +                     1:      speedbin 1
> > +                     2:      speedbin 2
> > +                     3-31:   unused
>
> I'm wondering if that's the right approach.
>
> I guess we could also have three different OPP tables, and pass them
> all three through a phandle array, and have the kernel code select
> which one is relevant based on the SID content

It's ok. But why not use the way we already have?
Is it necessary to introduce new helper?

>
> Another option would be to use the OF_DYNAMIC code to fill
> operating-points-v2 at kernel boot, before (or when) cpufreq kicks in.

My thought is to keep the same with others. And this situation may
make thingis complex though it works.

Hi  vireshk,

I want to hear from you.

Yours,
Yangtao

>
> ATF could also do that work.
>
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
Maxime Ripard April 9, 2019, 8:09 a.m. UTC | #4
On Tue, Apr 09, 2019 at 12:13:58AM +0800, Frank Lee wrote:
> On Fri, Apr 5, 2019 at 10:55 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > Hi,
> >
> > On Fri, Apr 05, 2019 at 06:24:55AM -0400, Yangtao Li wrote:
> > > Allwinner Process Voltage Scaling Tables defines the voltage and
> > > frequency value  based on the speedbin blown in the efuse combination.
> > > The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to
> > > provide the OPP framework with required information.
> > > This is used to determine the voltage and frequency value for each
> > > OPP of operating-points-v2 table when it is parsed by the OPP framework.
> > >
> > > This change adds documentation for the DT bindings.
> > > The "operating-points-v2-sunxi-cpu" DT extends the "operating-points-v2"
> > > with following parameters:
> > > - nvmem-cells (NVMEM area containig the speedbin information)
> > > - opp-supported-hw: A single 32 bit bitmap value,
> > >   representing compatible HW:
> > >                       0:      speedbin 0
> > >                       1:      speedbin 1
> > >                       2:      speedbin 2
> > >                       3-31:   unused
> > >
> > > Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
> > > ---
> > >  .../bindings/opp/sunxi-nvmem-cpufreq.txt      | 235 ++++++++++++++++++
> > >  1 file changed, 235 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
> > >
> > > diff --git a/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
> > > new file mode 100644
> > > index 000000000000..80201d4e5147
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
> > > @@ -0,0 +1,235 @@
> > > +Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings
> > > +===================================
> > > +
> > > +For some SoCs, the CPU frequency subset and voltage value of each OPP
> > > +varies based on the silicon variant in use. Allwinner Process Voltage
> > > +Scaling Tables defines the voltage and frequency value  based on the
> > > +speedbin blown in the efuse combination. The sunxi-cpufreq-nvmem driver
> > > +reads the efuse value from the SoC to provide the OPP framework with
> > > +required information.
> > > +
> > > +Required properties:
> > > +--------------------
> > > +In 'cpus' nodes:
> > > +- operating-points-v2: Phandle to the operating-points-v2 table to use.
> > > +
> > > +In 'operating-points-v2' table:
> > > +- compatible: Should be
> > > +     - 'operating-points-v2-sunxi-cpu'.
> > > +- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
> > > +             efuse registers that has information about the
> > > +             speedbin that is used to select the right frequency/voltage
> > > +             value pair.
> > > +             Please refer the for nvmem-cells
> > > +             bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
> > > +             and also examples below.
> > > +
> > > +In every OPP node:
> > > +- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
> > > +                 Bitmap:
> > > +                     0:      speedbin 0
> > > +                     1:      speedbin 1
> > > +                     2:      speedbin 2
> > > +                     3-31:   unused
> >
> > I'm wondering if that's the right approach.
> >
> > I guess we could also have three different OPP tables, and pass them
> > all three through a phandle array, and have the kernel code select
> > which one is relevant based on the SID content
>
> It's ok. But why not use the way we already have?
> Is it necessary to introduce new helper?

My main concern is that it becomes quite difficult to differentiate
the various OPPs, and to which bin a particular OPP is belonging to,
while the more traditional OPPv2 makes it much more obvious.

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Viresh Kumar April 9, 2019, 10:07 a.m. UTC | #5
On 05-04-19, 06:24, Yangtao Li wrote:
> +++ b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0>;
> +			enable-method = "psci";
> +			clocks = <&ccu CLK_CPUX>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
> +		};
> +
> +		cpu1: cpu@1 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <1>;
> +			enable-method = "psci";
> +			clocks = <&ccu CLK_CPUX>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
> +		};
> +
> +		cpu2: cpu@2 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <2>;
> +			enable-method = "psci";
> +			clocks = <&ccu CLK_CPUX>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
> +		};
> +
> +		cpu3: cpu@3 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <3>;
> +			enable-method = "psci";
> +			clocks = <&ccu CLK_CPUX>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +			operating-points-v2 = <&cpu_opp_table>;
> +			#cooling-cells = <2>;
> +		};
> +        };
> +
> +	cpu_opp_table: opp_table {
> +		compatible = "operating-points-v2-sunxi-cpu";
> +		nvmem-cells = <&speedbin_efuse>;
> +		opp-shared;
> +
> +		opp-480000000-0 {
> +			opp-hz = /bits/ 64 <480000000>;
> +			opp-microvolt = <880000>;
> +			opp-supported-hw = <0x1>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-720000000-0 {
> +			opp-hz = /bits/ 64 <720000000>;
> +			opp-microvolt = <880000>;
> +			opp-supported-hw = <0x1>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-816000000-0 {
> +			opp-hz = /bits/ 64 <816000000>;
> +			opp-microvolt = <880000>;
> +			opp-supported-hw = <0x1>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-888000000-0 {
> +			opp-hz = /bits/ 64 <888000000>;
> +			opp-microvolt = <940000>;
> +			opp-supported-hw = <0x1>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-1080000000-0 {
> +			opp-hz = /bits/ 64 <1080000000>;
> +			opp-microvolt = <1060000>;
> +			opp-supported-hw = <0x1>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-1320000000-0 {
> +			opp-hz = /bits/ 64 <1320000000>;
> +			opp-microvolt = <1160000>;
> +			opp-supported-hw = <0x1>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-1488000000-0 {
> +			opp-hz = /bits/ 64 <1488000000>;
> +			opp-microvolt = <1160000>;
> +			opp-supported-hw = <0x1>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp-480000000-1 {
> +			opp-hz = /bits/ 64 <480000000>;
> +			opp-microvolt = <820000>;
> +			opp-supported-hw = <0x2>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-720000000-1 {
> +			opp-hz = /bits/ 64 <720000000>;
> +			opp-microvolt = <820000>;
> +			opp-supported-hw = <0x2>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-816000000-1 {
> +			opp-hz = /bits/ 64 <816000000>;
> +			opp-microvolt = <820000>;
> +			opp-supported-hw = <0x2>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-888000000-1 {
> +			opp-hz = /bits/ 64 <888000000>;
> +			opp-microvolt = <820000>;
> +			opp-supported-hw = <0x2>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-1080000000-1 {
> +			opp-hz = /bits/ 64 <1080000000>;
> +			opp-microvolt = <880000>;
> +			opp-supported-hw = <0x2>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-1320000000-1 {
> +			opp-hz = /bits/ 64 <1320000000>;
> +			opp-microvolt = <940000>;
> +			opp-supported-hw = <0x2>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-1488000000-1 {
> +			opp-hz = /bits/ 64 <1488000000>;
> +			opp-microvolt = <1000000>;
> +			opp-supported-hw = <0x2>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +
> +		opp-480000000-2 {
> +			opp-hz = /bits/ 64 <480000000>;
> +			opp-microvolt = <800000>;
> +			opp-supported-hw = <0x4>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-720000000-2 {
> +			opp-hz = /bits/ 64 <720000000>;
> +			opp-microvolt = <800000>;
> +			opp-supported-hw = <0x4>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-816000000-2 {
> +			opp-hz = /bits/ 64 <816000000>;
> +			opp-microvolt = <800000>;
> +			opp-supported-hw = <0x4>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-888000000-2 {
> +			opp-hz = /bits/ 64 <888000000>;
> +			opp-microvolt = <800000>;
> +			opp-supported-hw = <0x4>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-1080000000-2 {
> +			opp-hz = /bits/ 64 <1080000000>;
> +			opp-microvolt = <840000>;
> +			opp-supported-hw = <0x4>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-1320000000-2 {
> +			opp-hz = /bits/ 64 <1320000000>;
> +			opp-microvolt = <900000>;
> +			opp-supported-hw = <0x4>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +		opp-1488000000-2 {
> +			opp-hz = /bits/ 64 <1488000000>;
> +			opp-microvolt = <960000>;
> +			opp-supported-hw = <0x4>;
> +			clock-latency-ns = <244144>; /* 8 32k periods */
> +		};
> +	};

Well, this is pure duplication of all the OPPs which isn't great. If I have
understood things correctly from the above example, then all you want is a
different microvolt value for each OPP, right ?

Then you are using the wrong feature of OPP core I am afraid. What you should
rather look for is opp-microvolt-<name> property, look in opp.txt bindings.

And these are the helper you need to use:
dev_pm_opp_set_prop_name()/dev_pm_opp_put_prop_name().
Frank Lee April 9, 2019, 5:34 p.m. UTC | #6
On Tue, Apr 9, 2019 at 6:07 PM Viresh Kumar <viresh.kumar@linaro.org> wrote:
>
> On 05-04-19, 06:24, Yangtao Li wrote:
> > +++ b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
> > +     cpus {
> > +             #address-cells = <1>;
> > +             #size-cells = <0>;
> > +
> > +             cpu0: cpu@0 {
> > +                     compatible = "arm,cortex-a53";
> > +                     device_type = "cpu";
> > +                     reg = <0>;
> > +                     enable-method = "psci";
> > +                     clocks = <&ccu CLK_CPUX>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     operating-points-v2 = <&cpu_opp_table>;
> > +                     #cooling-cells = <2>;
> > +             };
> > +
> > +             cpu1: cpu@1 {
> > +                     compatible = "arm,cortex-a53";
> > +                     device_type = "cpu";
> > +                     reg = <1>;
> > +                     enable-method = "psci";
> > +                     clocks = <&ccu CLK_CPUX>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     operating-points-v2 = <&cpu_opp_table>;
> > +                     #cooling-cells = <2>;
> > +             };
> > +
> > +             cpu2: cpu@2 {
> > +                     compatible = "arm,cortex-a53";
> > +                     device_type = "cpu";
> > +                     reg = <2>;
> > +                     enable-method = "psci";
> > +                     clocks = <&ccu CLK_CPUX>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     operating-points-v2 = <&cpu_opp_table>;
> > +                     #cooling-cells = <2>;
> > +             };
> > +
> > +             cpu3: cpu@3 {
> > +                     compatible = "arm,cortex-a53";
> > +                     device_type = "cpu";
> > +                     reg = <3>;
> > +                     enable-method = "psci";
> > +                     clocks = <&ccu CLK_CPUX>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +                     operating-points-v2 = <&cpu_opp_table>;
> > +                     #cooling-cells = <2>;
> > +             };
> > +        };
> > +
> > +     cpu_opp_table: opp_table {
> > +             compatible = "operating-points-v2-sunxi-cpu";
> > +             nvmem-cells = <&speedbin_efuse>;
> > +             opp-shared;
> > +
> > +             opp-480000000-0 {
> > +                     opp-hz = /bits/ 64 <480000000>;
> > +                     opp-microvolt = <880000>;
> > +                     opp-supported-hw = <0x1>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-720000000-0 {
> > +                     opp-hz = /bits/ 64 <720000000>;
> > +                     opp-microvolt = <880000>;
> > +                     opp-supported-hw = <0x1>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-816000000-0 {
> > +                     opp-hz = /bits/ 64 <816000000>;
> > +                     opp-microvolt = <880000>;
> > +                     opp-supported-hw = <0x1>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-888000000-0 {
> > +                     opp-hz = /bits/ 64 <888000000>;
> > +                     opp-microvolt = <940000>;
> > +                     opp-supported-hw = <0x1>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-1080000000-0 {
> > +                     opp-hz = /bits/ 64 <1080000000>;
> > +                     opp-microvolt = <1060000>;
> > +                     opp-supported-hw = <0x1>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-1320000000-0 {
> > +                     opp-hz = /bits/ 64 <1320000000>;
> > +                     opp-microvolt = <1160000>;
> > +                     opp-supported-hw = <0x1>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-1488000000-0 {
> > +                     opp-hz = /bits/ 64 <1488000000>;
> > +                     opp-microvolt = <1160000>;
> > +                     opp-supported-hw = <0x1>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp-480000000-1 {
> > +                     opp-hz = /bits/ 64 <480000000>;
> > +                     opp-microvolt = <820000>;
> > +                     opp-supported-hw = <0x2>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-720000000-1 {
> > +                     opp-hz = /bits/ 64 <720000000>;
> > +                     opp-microvolt = <820000>;
> > +                     opp-supported-hw = <0x2>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-816000000-1 {
> > +                     opp-hz = /bits/ 64 <816000000>;
> > +                     opp-microvolt = <820000>;
> > +                     opp-supported-hw = <0x2>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-888000000-1 {
> > +                     opp-hz = /bits/ 64 <888000000>;
> > +                     opp-microvolt = <820000>;
> > +                     opp-supported-hw = <0x2>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-1080000000-1 {
> > +                     opp-hz = /bits/ 64 <1080000000>;
> > +                     opp-microvolt = <880000>;
> > +                     opp-supported-hw = <0x2>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-1320000000-1 {
> > +                     opp-hz = /bits/ 64 <1320000000>;
> > +                     opp-microvolt = <940000>;
> > +                     opp-supported-hw = <0x2>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-1488000000-1 {
> > +                     opp-hz = /bits/ 64 <1488000000>;
> > +                     opp-microvolt = <1000000>;
> > +                     opp-supported-hw = <0x2>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +
> > +             opp-480000000-2 {
> > +                     opp-hz = /bits/ 64 <480000000>;
> > +                     opp-microvolt = <800000>;
> > +                     opp-supported-hw = <0x4>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-720000000-2 {
> > +                     opp-hz = /bits/ 64 <720000000>;
> > +                     opp-microvolt = <800000>;
> > +                     opp-supported-hw = <0x4>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-816000000-2 {
> > +                     opp-hz = /bits/ 64 <816000000>;
> > +                     opp-microvolt = <800000>;
> > +                     opp-supported-hw = <0x4>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-888000000-2 {
> > +                     opp-hz = /bits/ 64 <888000000>;
> > +                     opp-microvolt = <800000>;
> > +                     opp-supported-hw = <0x4>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-1080000000-2 {
> > +                     opp-hz = /bits/ 64 <1080000000>;
> > +                     opp-microvolt = <840000>;
> > +                     opp-supported-hw = <0x4>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-1320000000-2 {
> > +                     opp-hz = /bits/ 64 <1320000000>;
> > +                     opp-microvolt = <900000>;
> > +                     opp-supported-hw = <0x4>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +             opp-1488000000-2 {
> > +                     opp-hz = /bits/ 64 <1488000000>;
> > +                     opp-microvolt = <960000>;
> > +                     opp-supported-hw = <0x4>;
> > +                     clock-latency-ns = <244144>; /* 8 32k periods */
> > +             };
> > +     };
>
> Well, this is pure duplication of all the OPPs which isn't great. If I have
> understood things correctly from the above example, then all you want is a
> different microvolt value for each OPP, right ?

Not exactly like this. But this is working for the current situation.

>
> Then you are using the wrong feature of OPP core I am afraid. What you should
> rather look for is opp-microvolt-<name> property, look in opp.txt bindings.

Yeah. This is more appropriate.

>
> And these are the helper you need to use:
> dev_pm_opp_set_prop_name()/dev_pm_opp_put_prop_name().

Thanks,
Yangtao

>
> --
> viresh
Frank Lee April 9, 2019, 5:49 p.m. UTC | #7
On Tue, Apr 9, 2019 at 4:10 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Tue, Apr 09, 2019 at 12:13:58AM +0800, Frank Lee wrote:
> > On Fri, Apr 5, 2019 at 10:55 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > >
> > > Hi,
> > >
> > > On Fri, Apr 05, 2019 at 06:24:55AM -0400, Yangtao Li wrote:
> > > > Allwinner Process Voltage Scaling Tables defines the voltage and
> > > > frequency value  based on the speedbin blown in the efuse combination.
> > > > The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to
> > > > provide the OPP framework with required information.
> > > > This is used to determine the voltage and frequency value for each
> > > > OPP of operating-points-v2 table when it is parsed by the OPP framework.
> > > >
> > > > This change adds documentation for the DT bindings.
> > > > The "operating-points-v2-sunxi-cpu" DT extends the "operating-points-v2"
> > > > with following parameters:
> > > > - nvmem-cells (NVMEM area containig the speedbin information)
> > > > - opp-supported-hw: A single 32 bit bitmap value,
> > > >   representing compatible HW:
> > > >                       0:      speedbin 0
> > > >                       1:      speedbin 1
> > > >                       2:      speedbin 2
> > > >                       3-31:   unused
> > > >
> > > > Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
> > > > ---
> > > >  .../bindings/opp/sunxi-nvmem-cpufreq.txt      | 235 ++++++++++++++++++
> > > >  1 file changed, 235 insertions(+)
> > > >  create mode 100644 Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
> > > > new file mode 100644
> > > > index 000000000000..80201d4e5147
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
> > > > @@ -0,0 +1,235 @@
> > > > +Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings
> > > > +===================================
> > > > +
> > > > +For some SoCs, the CPU frequency subset and voltage value of each OPP
> > > > +varies based on the silicon variant in use. Allwinner Process Voltage
> > > > +Scaling Tables defines the voltage and frequency value  based on the
> > > > +speedbin blown in the efuse combination. The sunxi-cpufreq-nvmem driver
> > > > +reads the efuse value from the SoC to provide the OPP framework with
> > > > +required information.
> > > > +
> > > > +Required properties:
> > > > +--------------------
> > > > +In 'cpus' nodes:
> > > > +- operating-points-v2: Phandle to the operating-points-v2 table to use.
> > > > +
> > > > +In 'operating-points-v2' table:
> > > > +- compatible: Should be
> > > > +     - 'operating-points-v2-sunxi-cpu'.
> > > > +- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
> > > > +             efuse registers that has information about the
> > > > +             speedbin that is used to select the right frequency/voltage
> > > > +             value pair.
> > > > +             Please refer the for nvmem-cells
> > > > +             bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
> > > > +             and also examples below.
> > > > +
> > > > +In every OPP node:
> > > > +- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
> > > > +                 Bitmap:
> > > > +                     0:      speedbin 0
> > > > +                     1:      speedbin 1
> > > > +                     2:      speedbin 2
> > > > +                     3-31:   unused
> > >
> > > I'm wondering if that's the right approach.
> > >
> > > I guess we could also have three different OPP tables, and pass them
> > > all three through a phandle array, and have the kernel code select
> > > which one is relevant based on the SID content
> >
> > It's ok. But why not use the way we already have?
> > Is it necessary to introduce new helper?
>
> My main concern is that it becomes quite difficult to differentiate
> the various OPPs, and to which bin a particular OPP is belonging to,
> while the more traditional OPPv2 makes it much more obvious.
Hi Maxime,

How about the newer patch ?
I think it is clearer. Just add a printk and people will know the opp
information used.

Yangtao
>
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com

Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
new file mode 100644
index 000000000000..80201d4e5147
--- /dev/null
+++ b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
@@ -0,0 +1,235 @@ 
+Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings
+===================================
+
+For some SoCs, the CPU frequency subset and voltage value of each OPP
+varies based on the silicon variant in use. Allwinner Process Voltage
+Scaling Tables defines the voltage and frequency value  based on the
+speedbin blown in the efuse combination. The sunxi-cpufreq-nvmem driver
+reads the efuse value from the SoC to provide the OPP framework with
+required information.
+
+Required properties:
+--------------------
+In 'cpus' nodes:
+- operating-points-v2: Phandle to the operating-points-v2 table to use.
+
+In 'operating-points-v2' table:
+- compatible: Should be
+	- 'operating-points-v2-sunxi-cpu'.
+- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
+		efuse registers that has information about the
+		speedbin that is used to select the right frequency/voltage
+		value pair.
+		Please refer the for nvmem-cells
+		bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
+		and also examples below.
+
+In every OPP node:
+- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
+		    Bitmap:
+			0:	speedbin 0
+			1:	speedbin 1
+			2:	speedbin 2
+			3-31:	unused
+
+Example 1:
+---------
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0>;
+			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <1>;
+			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+		};
+
+		cpu2: cpu@2 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <2>;
+			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+		};
+
+		cpu3: cpu@3 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <3>;
+			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+		};
+        };
+
+	cpu_opp_table: opp_table {
+		compatible = "operating-points-v2-sunxi-cpu";
+		nvmem-cells = <&speedbin_efuse>;
+		opp-shared;
+
+		opp-480000000-0 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <880000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-720000000-0 {
+			opp-hz = /bits/ 64 <720000000>;
+			opp-microvolt = <880000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-816000000-0 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <880000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-888000000-0 {
+			opp-hz = /bits/ 64 <888000000>;
+			opp-microvolt = <940000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1080000000-0 {
+			opp-hz = /bits/ 64 <1080000000>;
+			opp-microvolt = <1060000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1320000000-0 {
+			opp-hz = /bits/ 64 <1320000000>;
+			opp-microvolt = <1160000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1488000000-0 {
+			opp-hz = /bits/ 64 <1488000000>;
+			opp-microvolt = <1160000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp-480000000-1 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <820000>;
+			opp-supported-hw = <0x2>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-720000000-1 {
+			opp-hz = /bits/ 64 <720000000>;
+			opp-microvolt = <820000>;
+			opp-supported-hw = <0x2>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-816000000-1 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <820000>;
+			opp-supported-hw = <0x2>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-888000000-1 {
+			opp-hz = /bits/ 64 <888000000>;
+			opp-microvolt = <820000>;
+			opp-supported-hw = <0x2>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1080000000-1 {
+			opp-hz = /bits/ 64 <1080000000>;
+			opp-microvolt = <880000>;
+			opp-supported-hw = <0x2>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1320000000-1 {
+			opp-hz = /bits/ 64 <1320000000>;
+			opp-microvolt = <940000>;
+			opp-supported-hw = <0x2>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1488000000-1 {
+			opp-hz = /bits/ 64 <1488000000>;
+			opp-microvolt = <1000000>;
+			opp-supported-hw = <0x2>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp-480000000-2 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <800000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-720000000-2 {
+			opp-hz = /bits/ 64 <720000000>;
+			opp-microvolt = <800000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-816000000-2 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <800000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-888000000-2 {
+			opp-hz = /bits/ 64 <888000000>;
+			opp-microvolt = <800000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1080000000-2 {
+			opp-hz = /bits/ 64 <1080000000>;
+			opp-microvolt = <840000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1320000000-2 {
+			opp-hz = /bits/ 64 <1320000000>;
+			opp-microvolt = <900000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1488000000-2 {
+			opp-hz = /bits/ 64 <1488000000>;
+			opp-microvolt = <960000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+	};
+
+....
+soc {
+....
+	sid: sid@3006000 {
+		compatible = "allwinner,sun50i-h6-sid";
+		reg = <0x03006000 0x400>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		....
+		speedbin_efuse: speed@1c {
+			reg = <0x1c 4>;
+		};
+        };
+};