From patchwork Fri Apr 5 14:26:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 10887497 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0CC67922 for ; Fri, 5 Apr 2019 14:28:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E51C3286E5 for ; Fri, 5 Apr 2019 14:28:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D53AB28AF7; Fri, 5 Apr 2019 14:28:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5B345286E5 for ; Fri, 5 Apr 2019 14:28:28 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hCPna-0007Rz-Ay; Fri, 05 Apr 2019 14:26:30 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hCPnY-0007Ro-St for xen-devel@lists.xenproject.org; Fri, 05 Apr 2019 14:26:28 +0000 X-Inumbo-ID: cbda75ef-57ae-11e9-92d7-bc764e045a96 Received: from prv1-mh.provo.novell.com (unknown [137.65.248.33]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id cbda75ef-57ae-11e9-92d7-bc764e045a96; Fri, 05 Apr 2019 14:26:27 +0000 (UTC) Received: from INET-PRV1-MTA by prv1-mh.provo.novell.com with Novell_GroupWise; Fri, 05 Apr 2019 08:26:26 -0600 Message-Id: <5CA765920200007800224E5A@prv1-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 18.1.0 Date: Fri, 05 Apr 2019 08:26:26 -0600 From: "Jan Beulich" To: "xen-devel" References: <5CA75E460200007800224E23@prv1-mh.provo.novell.com> In-Reply-To: <5CA75E460200007800224E23@prv1-mh.provo.novell.com> Mime-Version: 1.0 Content-Disposition: inline Subject: [Xen-devel] [PATCH v2 1/2] x86/AMD: correct certain Fam17 checks X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Brian Woods , Wei Liu , Pu Wen , Roger Pau Monne Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Commit 3157bb4e13 ("Add MSR support for various feature AMD processor families") converted certain checks for Fam11 to include families all the way up to Fam17. The commit having no description, it is hard to tell whether this was a mechanical dec->hex conversion mistake, or indeed intended. In any event the NB_CFG handling needs to be restricted to Fam16 and below: Fam17 doesn't really have such an MSR anymore. As per observation it's read-zero / write-discard now, so make PV uniformly (with the exception of pinned Dom0 vCPU-s) behave so, just like HVM already does. Mirror the NB_CFG behavior to MSR_FAM10H_MMIO_CONF_BASE as well, except that here the vendor/model check is kept in place (for now at least). A non-MMCFG extended config space access mechanism still appears to exist, but code to deal with it will need to be written down the road, when it can actually be tested. Reported-by: Pu Wen Signed-off-by: Jan Beulich Acked-by: Andrew Cooper --- v2: Make NB_CFG read-zero / write-discard for PV DomU, just like HVM has it already. I've not applied "In principle, Acked-by: Andrew Cooper ". --- a/xen/arch/x86/hvm/ioreq.c +++ b/xen/arch/x86/hvm/ioreq.c @@ -1288,7 +1288,7 @@ struct hvm_ioreq_server *hvm_select_iore d->arch.cpuid->x86_vendor == X86_VENDOR_AMD && (x86_fam = get_cpu_family( d->arch.cpuid->basic.raw_fms, NULL, NULL)) > 0x10 && - x86_fam <= 0x17 ) + x86_fam < 0x17 ) { uint64_t msr_val; --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -195,7 +195,7 @@ static bool pci_cfg_ok(struct domain *cu /* AMD extended configuration space access? */ if ( CF8_ADDR_HI(currd->arch.pci_cf8) && boot_cpu_data.x86_vendor == X86_VENDOR_AMD && - boot_cpu_data.x86 >= 0x10 && boot_cpu_data.x86 <= 0x17 ) + boot_cpu_data.x86 >= 0x10 && boot_cpu_data.x86 < 0x17 ) { uint64_t msr_val; @@ -893,6 +893,17 @@ static int read_msr(unsigned int reg, ui *val = 0; return X86EMUL_OKAY; + case MSR_FAM10H_MMIO_CONF_BASE: + if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD || + boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 >= 0x17 ) + break; + /* fall through */ + case MSR_AMD64_NB_CFG: + if ( is_hwdom_pinned_vcpu(curr) ) + goto normal; + *val = 0; + return X86EMUL_OKAY; + case MSR_IA32_MISC_ENABLE: rdmsrl(reg, *val); *val = guest_misc_enable(*val); @@ -1003,9 +1014,6 @@ static int write_msr(unsigned int reg, u break; case MSR_AMD64_NB_CFG: - if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD || - boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 ) - break; if ( !is_hwdom_pinned_vcpu(curr) ) return X86EMUL_OKAY; if ( (rdmsr_safe(MSR_AMD64_NB_CFG, temp) != 0) || @@ -1017,7 +1025,7 @@ static int write_msr(unsigned int reg, u case MSR_FAM10H_MMIO_CONF_BASE: if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD || - boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 ) + boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 >= 0x17 ) break; if ( !is_hwdom_pinned_vcpu(curr) ) return X86EMUL_OKAY;