diff mbox series

[31/31,v3] ARM: dts: Add queue manager and NPE to the IXP4xx DTSI

Message ID 20190408062831.16422-32-linus.walleij@linaro.org (mailing list archive)
State New, archived
Headers show
Series ARM: ixp4xx: Modernize and DT support | expand

Commit Message

Linus Walleij April 8, 2019, 6:28 a.m. UTC 
The AHB queue manager and Network Processing Engines are
present on all IXP4xx SoCs, so we add them to the overarching
device tree include.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Rebased on v5.1-rc1
---
 arch/arm/boot/dts/intel-ixp4xx.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi
index 9edd49509af8..96a5a02f7ba9 100644
--- a/arch/arm/boot/dts/intel-ixp4xx.dtsi
+++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi
@@ -14,6 +14,13 @@ 
 		compatible = "simple-bus";
 		interrupt-parent = <&intcon>;
 
+		qmgr: queue-manager@60000000 {
+			compatible = "intel,ixp4xx-ahb-queue-manager";
+			reg = <0x60000000 0x4000>;
+			#queue-cells = <1>;
+			interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		uart0: serial@c8000000 {
 			compatible = "intel,xscale-uart";
 			reg = <0xc8000000 0x1000>;
@@ -54,5 +61,10 @@ 
 			reg = <0xc8005000 0x100>;
 			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		npe@c8006000 {
+			compatible = "intel,ixp4xx-network-processing-engine";
+			reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
+		};
 	};
 };