@@ -239,8 +239,9 @@ static inline struct clk *mpc512x_clk_divider(
const char *name, const char *parent_name, u8 clkflags,
u32 __iomem *reg, u8 pos, u8 len, int divflags)
{
- return clk_register_divider(NULL, name, parent_name, clkflags,
- reg, pos, len, divflags, &clklock);
+ return clk_register_divider(NULL, name, parent_name,
+ clkflags | CLK_IS_BIG_ENDIAN, reg, pos, len,
+ divflags, &clklock);
}
static inline struct clk *mpc512x_clk_divtable(
@@ -248,10 +249,12 @@ static inline struct clk *mpc512x_clk_divtable(
u32 __iomem *reg, u8 pos, u8 len,
const struct clk_div_table *divtab)
{
+ int clkflags;
u8 divflags;
+ clkflags = CLK_IS_BIG_ENDIAN;
divflags = 0;
- return clk_register_divider_table(NULL, name, parent_name, 0,
+ return clk_register_divider_table(NULL, name, parent_name, clkflags,
reg, pos, len, divflags,
divtab, &clklock);
}
@@ -262,7 +265,7 @@ static inline struct clk *mpc512x_clk_gated(
{
int clkflags;
- clkflags = CLK_SET_RATE_PARENT;
+ clkflags = CLK_SET_RATE_PARENT | CLK_IS_BIG_ENDIAN;
return clk_register_gate(NULL, name, parent_name, clkflags,
reg, pos, 0, &clklock);
}
@@ -274,7 +277,7 @@ static inline struct clk *mpc512x_clk_muxed(const char *name,
int clkflags;
u8 muxflags;
- clkflags = CLK_SET_RATE_PARENT;
+ clkflags = CLK_SET_RATE_PARENT | CLK_IS_BIG_ENDIAN;
muxflags = 0;
return clk_register_mux(NULL, name,
parent_names, parent_count, clkflags,
These clocks' registers are accessed as big endian, so mark them as such. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> --- arch/powerpc/platforms/512x/clock-commonclk.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-)