| Message ID | 1554888341-5249-1-git-send-email-jjian.zhou@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: mt8183: add mmc node | expand |
On 10/04/2019 11:25, Jjian Zhou wrote: > From: jjian zhou <jjian.zhou@mediatek.com> > > Add mmc DTS node to the mt8183 and mt8183-evb. > > Signed-off-by: Jjian Zhou <jjian.zhou@mediatek.com> > --- > This patch is based on v5.1-rc1 and these patches: > http://lists.infradead.org/pipermail/linux-mediatek/2019-March/017963.html > https://patchwork.kernel.org/patch/10856987/ > https://patchwork.kernel.org/cover/10879001/ > https://patchwork.kernel.org/cover/10846677/ These requirements are now fulfilled. Applied now to v5.7-next/dts64 Thanks! > --- > arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 149 ++++++++++++++++++++++++++++ > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 24 +++++ > 2 files changed, 173 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > index 9b52559..465cdab 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > @@ -7,6 +7,7 @@ > > /dts-v1/; > #include "mt8183.dtsi" > +#include "mt6358.dtsi" > > / { > model = "MediaTek MT8183 evaluation board"; > @@ -26,6 +27,154 @@ > }; > }; > > +&mmc0 { > + status = "okay"; > + pinctrl-names = "default", "state_uhs"; > + pinctrl-0 = <&mmc0_pins_default>; > + pinctrl-1 = <&mmc0_pins_uhs>; > + bus-width = <8>; > + max-frequency = <200000000>; > + cap-mmc-highspeed; > + mmc-hs200-1_8v; > + mmc-hs400-1_8v; > + cap-mmc-hw-reset; > + no-sdio; > + no-sd; > + hs400-ds-delay = <0x12814>; > + vmmc-supply = <&mt6358_vemc_reg>; > + vqmmc-supply = <&mt6358_vio18_reg>; > + assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; > + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; > + non-removable; > +}; > + > +&mmc1 { > + status = "okay"; > + pinctrl-names = "default", "state_uhs"; > + pinctrl-0 = <&mmc1_pins_default>; > + pinctrl-1 = <&mmc1_pins_uhs>; > + bus-width = <4>; > + max-frequency = <200000000>; > + cap-sd-highspeed; > + sd-uhs-sdr50; > + sd-uhs-sdr104; > + cap-sdio-irq; > + no-mmc; > + no-sd; > + vmmc-supply = <&mt6358_vmch_reg>; > + vqmmc-supply = <&mt6358_vmc_reg>; > + keep-power-in-suspend; > + enable-sdio-wakeup; > + non-removable; > +}; > + > +&pio { > + mmc0_pins_default: mmc0default { > + pins_cmd_dat { > + pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, > + <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, > + <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, > + <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, > + <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, > + <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, > + <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, > + <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, > + <PINMUX_GPIO122__FUNC_MSDC0_CMD>; > + input-enable; > + bias-pull-up; > + }; > + > + pins_clk { > + pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; > + bias-pull-down; > + }; > + > + pins_rst { > + pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; > + bias-pull-up; > + }; > + }; > + > + mmc0_pins_uhs: mmc0@0{ > + pins_cmd_dat { > + pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, > + <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, > + <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, > + <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, > + <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, > + <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, > + <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, > + <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, > + <PINMUX_GPIO122__FUNC_MSDC0_CMD>; > + input-enable; > + drive-strength = <MTK_DRIVE_10mA>; > + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; > + }; > + > + pins_clk { > + pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; > + drive-strength = <MTK_DRIVE_10mA>; > + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; > + }; > + > + pins_ds { > + pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; > + drive-strength = <MTK_DRIVE_10mA>; > + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; > + }; > + > + pins_rst { > + pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; > + drive-strength = <MTK_DRIVE_10mA>; > + bias-pull-up; > + }; > + }; > + > + mmc1_pins_default: mmc1default { > + pins_cmd_dat { > + pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, > + <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, > + <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, > + <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, > + <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; > + input-enable; > + bias-pull-up; > + }; > + > + pins_clk { > + pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; > + input-enable; > + bias-pull-down; > + }; > + > + pins_pmu { > + pinmux = <PINMUX_GPIO178__FUNC_GPIO178>, > + <PINMUX_GPIO166__FUNC_GPIO166>; > + output-high; > + }; > + }; > + > + mmc1_pins_uhs: mmc1@0{ > + pins_cmd_dat { > + pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, > + <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, > + <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, > + <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, > + <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; > + drive-strength = <MTK_DRIVE_6mA>; > + input-enable; > + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; > + }; > + > + pins_clk { > + pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; > + drive-strength = <MTK_DRIVE_6mA>; > + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; > + input-enable; > + }; > + }; > +}; > + > &uart0 { > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 482e451..38cec41 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -273,6 +273,30 @@ > #clock-cells = <1>; > }; > > + mmc0: mmc@11230000 { > + compatible = "mediatek,mt8183-mmc"; > + reg = <0 0x11230000 0 0x1000>, > + <0 0x11f50000 0 0x1000>; > + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, > + <&infracfg CLK_INFRA_MSDC0>, > + <&infracfg CLK_INFRA_MSDC0_SCK>; > + clock-names = "source", "hclk", "source_cg"; > + status = "disabled"; > + }; > + > + mmc1: mmc@11240000 { > + compatible = "mediatek,mt8183-mmc"; > + reg = <0 0x11240000 0 0x1000>, > + <0 0x11e10000 0 0x1000>; > + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, > + <&infracfg CLK_INFRA_MSDC1>, > + <&infracfg CLK_INFRA_MSDC1_SCK>; > + clock-names = "source", "hclk", "source_cg"; > + status = "disabled"; > + }; > + > mfgcfg: syscon@13000000 { > compatible = "mediatek,mt8183-mfgcfg", "syscon"; > reg = <0 0x13000000 0 0x1000>; > -- > 1.9.1 >
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 9b52559..465cdab 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "mt8183.dtsi" +#include "mt6358.dtsi" / { model = "MediaTek MT8183 evaluation board"; @@ -26,6 +27,154 @@ }; }; +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x12814>; + vmmc-supply = <&mt6358_vemc_reg>; + vqmmc-supply = <&mt6358_vio18_reg>; + assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; + non-removable; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + cap-sdio-irq; + no-mmc; + no-sd; + vmmc-supply = <&mt6358_vmch_reg>; + vqmmc-supply = <&mt6358_vmc_reg>; + keep-power-in-suspend; + enable-sdio-wakeup; + non-removable; +}; + +&pio { + mmc0_pins_default: mmc0default { + pins_cmd_dat { + pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO122__FUNC_MSDC0_CMD>; + input-enable; + bias-pull-up; + }; + + pins_clk { + pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; + bias-pull-down; + }; + + pins_rst { + pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; + bias-pull-up; + }; + }; + + mmc0_pins_uhs: mmc0@0{ + pins_cmd_dat { + pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO122__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_10mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins_clk { + pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; + drive-strength = <MTK_DRIVE_10mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_ds { + pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; + drive-strength = <MTK_DRIVE_10mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_rst { + pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; + drive-strength = <MTK_DRIVE_10mA>; + bias-pull-up; + }; + }; + + mmc1_pins_default: mmc1default { + pins_cmd_dat { + pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, + <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; + input-enable; + bias-pull-up; + }; + + pins_clk { + pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; + input-enable; + bias-pull-down; + }; + + pins_pmu { + pinmux = <PINMUX_GPIO178__FUNC_GPIO178>, + <PINMUX_GPIO166__FUNC_GPIO166>; + output-high; + }; + }; + + mmc1_pins_uhs: mmc1@0{ + pins_cmd_dat { + pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, + <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; + drive-strength = <MTK_DRIVE_6mA>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins_clk { + pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + input-enable; + }; + }; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 482e451..38cec41 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -273,6 +273,30 @@ #clock-cells = <1>; }; + mmc0: mmc@11230000 { + compatible = "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11f50000 0 0x1000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, + <&infracfg CLK_INFRA_MSDC0>, + <&infracfg CLK_INFRA_MSDC0_SCK>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8183-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11e10000 0 0x1000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, + <&infracfg CLK_INFRA_MSDC1>, + <&infracfg CLK_INFRA_MSDC1_SCK>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + mfgcfg: syscon@13000000 { compatible = "mediatek,mt8183-mfgcfg", "syscon"; reg = <0 0x13000000 0 0x1000>;