[V2,1/2] ASoC: fsl_asrc: replace the process_option table with function
diff mbox series

Message ID a04859bff36ba26cb4cb51ff092a3f2e2eca455d.1554975348.git.shengjiu.wang@nxp.com
State New
Headers show
Series
  • Support more sample rate in asrc
Related show

Commit Message

Shengjiu Wang April 11, 2019, 9:39 a.m. UTC
When we want to support more sample rate, for example 12kHz/24kHz
we need update the process_option table, if we want to support more
sample rate next time, the table need to be updated again. which
is not flexible.

We got a function fsl_asrc_sel_proc to replace the table, which can
give the pre-processing and post-processing options according to
the sample rate.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
 sound/soc/fsl/fsl_asrc.c | 87 +++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 67 insertions(+), 20 deletions(-)

Comments

Daniel Baluta April 11, 2019, 11:15 a.m. UTC | #1
Hi Shengjiu,

Mostly looking good. See few comments inline:

<snip>

> +/*
> + * Select the pre-processing and post-processing options
> + *
> + * Fsin: input sample rate
> + * Fsout: output sample rate
> + * pre_proc: return value for pre-processing option
> + * post_proc: return value for post-processing option
> + */
> +static int fsl_asrc_sel_proc(int Fsin, int Fsout, int *pre_proc, int *post_proc)

Lets be naming consistent here: Fsin -> fs_in, Fsout -> fs_out.

> +{
> +       bool det_out_op2_cond;
> +       bool det_out_op0_cond;
> +
> +       /* Codition for selection of post-processing */
> +       det_out_op2_cond = (((Fsin * 15 > Fsout * 16) & (Fsout < 56000)) |
> +                                       ((Fsin > 56000) & (Fsout < 56000)));
Remove outer parenthesis. Also should here be a logical or (||)
instead of bitwise or (|)?
Same for && vs &.

> +       det_out_op0_cond = (Fsin * 23 < Fsout * 8);

Remove outer parenthesis.
> +
> +       /*
> +        * unsupported case: Tsout>16.125*Tsin, and Tsout>8.125*Tsin.
> +        * Tsout>16.125*Tsin -> Fsin * 8 > 129 * Fsout
> +        * Tsout>8.125*Tsin  -> Fsin * 8 > 65 * Fsout
> +        * Tsout>4.125*Tsin  -> Fsin * 8 > 33 * Fsout
> +        * Tsout>1.875*Tsin  -> Fsin * 8 > 15 * Fsout
> +        */
> +       if (Fsin * 8 > 129 * Fsout)
> +               *pre_proc = 5;
> +       else if (Fsin * 8 > 65 * Fsout)
> +               *pre_proc = 4;
> +       else if (Fsin * 8 > 33 * Fsout)
> +               *pre_proc = 2;
> +       else if (Fsin * 8 > 15 * Fsout) {
> +               if (Fsin > 152000)
> +                       *pre_proc = 2;
> +               else
> +                       *pre_proc = 1;
> +       } else if (Fsin < 76000)
> +               *pre_proc = 0;
> +       else if (Fsin > 152000)
> +               *pre_proc = 2;
> +       else
> +               *pre_proc = 1;
> +
> +       if (det_out_op2_cond)
> +               *post_proc = 2;
> +       else if (det_out_op0_cond)
> +               *post_proc = 0;
> +       else
> +               *post_proc = 1;
> +
> +       /* unsupported options */
> +       if (*pre_proc == 4 || *pre_proc == 5)
> +               return -EINVAL;
> +
> +       return 0;
> +}
> +
>  /**
>   * Request ASRC pair
>   *
> @@ -239,8 +278,10 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
>         u32 inrate, outrate, indiv, outdiv;
>         u32 clk_index[2], div[2];
>         int in, out, channels;
> +       int pre_proc, post_proc;
>         struct clk *clk;
>         bool ideal;
> +       int ret;
>
>         if (!config) {
>                 pair_err("invalid pair config\n");
> @@ -289,6 +330,12 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
>                 return -EINVAL;
>         }
>
> +       ret = fsl_asrc_sel_proc(inrate, outrate, &pre_proc, &post_proc);
> +       if (ret) {
> +               pair_err("No supported pre-processing options\n");
> +               return ret;
> +       }
> +
>         /* Validate input and output clock sources */
>         clk_index[IN] = clk_map[IN][config->inclk];
>         clk_index[OUT] = clk_map[OUT][config->outclk];
> @@ -380,8 +427,8 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
>         /* Apply configurations for pre- and post-processing */
>         regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
>                            ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index),
> -                          ASRCFG_PREMOD(index, process_option[in][out][0]) |
> -                          ASRCFG_POSTMOD(index, process_option[in][out][1]));
> +                          ASRCFG_PREMOD(index, pre_proc) |
> +                          ASRCFG_POSTMOD(index, post_proc));
>
>         return fsl_asrc_set_ideal_ratio(pair, inrate, outrate);
>  }
> --
> 1.9.1
>
Nicolin Chen April 11, 2019, 8:06 p.m. UTC | #2
On Thu, Apr 11, 2019 at 09:39:06AM +0000, S.j. Wang wrote:
  
> +/*
> + * Select the pre-processing and post-processing options

By aligning with other function comments:
/**
 * Select the pre-processing and post-processing options

> + *
> + * Fsin: input sample rate
> + * Fsout: output sample rate

I would suggest to use inrate and outrate to keep naming consistent.

> + * pre_proc: return value for pre-processing option
> + * post_proc: return value for post-processing option
> + */
> +static int fsl_asrc_sel_proc(int Fsin, int Fsout, int *pre_proc, int *post_proc)
> +{
> +	bool det_out_op2_cond;
> +	bool det_out_op0_cond;

By looking at the comments below. Probably better to rename them
	bool post_proc_cond2, post_proc_cond0;

> +	/* Codition for selection of post-processing */

"Codition" -> "Conditions"

> +	det_out_op2_cond = (((Fsin * 15 > Fsout * 16) & (Fsout < 56000)) |
> +					((Fsin > 56000) & (Fsout < 56000)));

Combining Daniel's comments + indentation alignment:
	det_out_op2_cond = (Fsin * 15 > Fsout * 16 && Fsout < 56000) ||
			   (Fsin > 56000 && Fsout < 56000);

> +	det_out_op0_cond = (Fsin * 23 < Fsout * 8);
> +
> +	/*
> +	 * unsupported case: Tsout>16.125*Tsin, and Tsout>8.125*Tsin.

Funny thing is that there'd be no point in checking the 16.125, if
Tsout is bigger than 8.125 times of Tsin, i.e. only one condition:
	Tsout > 8.125 * Tsin

> +	 * Tsout>16.125*Tsin -> Fsin * 8 > 129 * Fsout
> +	 * Tsout>8.125*Tsin  -> Fsin * 8 > 65 * Fsout
> +	 * Tsout>4.125*Tsin  -> Fsin * 8 > 33 * Fsout
> +	 * Tsout>1.875*Tsin  -> Fsin * 8 > 15 * Fsout

Took me a while to understand what it is saying....

Better to write like this:
	/* Does not support cases: Tsout > 8.125 * Tsin */
	if (Fsin * 8 > 65 * Fsout) {
		pair_err("Does not support %d > 8.125 * %d\n", Fsout, Fsin);
		return -EINVAL;
	}

	/* Otherwise, select pre_proc between [0, 2] */
	if (Fsin * 8 > 33 * Fsout)
> +		*pre_proc = 2;
> +	else if (Fsin * 8 > 15 * Fsout) {
> +		if (Fsin > 152000)
> +			*pre_proc = 2;
> +		else
> +			*pre_proc = 1;
> +	} else if (Fsin < 76000)
> +		*pre_proc = 0;
> +	else if (Fsin > 152000)
> +		*pre_proc = 2;
> +	else
> +		*pre_proc = 1;

<== Would look better by moving post_cond calculations here.

> +	if (det_out_op2_cond)
> +		*post_proc = 2;
> +	else if (det_out_op0_cond)
> +		*post_proc = 0;
> +	else
> +		*post_proc = 1;

And we could remove this check below:
> +	/* unsupported options */
> +	if (*pre_proc == 4 || *pre_proc == 5)
> +		return -EINVAL;

So basically we are doing:
	1) Error out unsupported cases
	2) Select pre_proc
	3) Calculate conditions for post_proc
	4) Select post_proc

Thanks

Patch
diff mbox series

diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c
index 0b937924d2e4..5857d383d962 100644
--- a/sound/soc/fsl/fsl_asrc.c
+++ b/sound/soc/fsl/fsl_asrc.c
@@ -26,24 +26,6 @@ 
 #define pair_dbg(fmt, ...) \
 	dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
 
-/* Sample rates are aligned with that defined in pcm.h file */
-static const u8 process_option[][12][2] = {
-	/* 8kHz 11.025kHz 16kHz 22.05kHz 32kHz 44.1kHz 48kHz   64kHz   88.2kHz 96kHz   176kHz  192kHz */
-	{{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},	/* 5512Hz */
-	{{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},	/* 8kHz */
-	{{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},	/* 11025Hz */
-	{{1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},	/* 16kHz */
-	{{1, 2}, {1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},	/* 22050Hz */
-	{{1, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},},	/* 32kHz */
-	{{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},},	/* 44.1kHz */
-	{{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},},	/* 48kHz */
-	{{2, 2}, {2, 2}, {2, 2}, {2, 1}, {1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},},	/* 64kHz */
-	{{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},},	/* 88.2kHz */
-	{{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},},	/* 96kHz */
-	{{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},},	/* 176kHz */
-	{{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},},	/* 192kHz */
-};
-
 /* Corresponding to process_option */
 static int supported_input_rate[] = {
 	5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200,
@@ -79,6 +61,63 @@ 
 
 static unsigned char *clk_map[2];
 
+/*
+ * Select the pre-processing and post-processing options
+ *
+ * Fsin: input sample rate
+ * Fsout: output sample rate
+ * pre_proc: return value for pre-processing option
+ * post_proc: return value for post-processing option
+ */
+static int fsl_asrc_sel_proc(int Fsin, int Fsout, int *pre_proc, int *post_proc)
+{
+	bool det_out_op2_cond;
+	bool det_out_op0_cond;
+
+	/* Codition for selection of post-processing */
+	det_out_op2_cond = (((Fsin * 15 > Fsout * 16) & (Fsout < 56000)) |
+					((Fsin > 56000) & (Fsout < 56000)));
+	det_out_op0_cond = (Fsin * 23 < Fsout * 8);
+
+	/*
+	 * unsupported case: Tsout>16.125*Tsin, and Tsout>8.125*Tsin.
+	 * Tsout>16.125*Tsin -> Fsin * 8 > 129 * Fsout
+	 * Tsout>8.125*Tsin  -> Fsin * 8 > 65 * Fsout
+	 * Tsout>4.125*Tsin  -> Fsin * 8 > 33 * Fsout
+	 * Tsout>1.875*Tsin  -> Fsin * 8 > 15 * Fsout
+	 */
+	if (Fsin * 8 > 129 * Fsout)
+		*pre_proc = 5;
+	else if (Fsin * 8 > 65 * Fsout)
+		*pre_proc = 4;
+	else if (Fsin * 8 > 33 * Fsout)
+		*pre_proc = 2;
+	else if (Fsin * 8 > 15 * Fsout) {
+		if (Fsin > 152000)
+			*pre_proc = 2;
+		else
+			*pre_proc = 1;
+	} else if (Fsin < 76000)
+		*pre_proc = 0;
+	else if (Fsin > 152000)
+		*pre_proc = 2;
+	else
+		*pre_proc = 1;
+
+	if (det_out_op2_cond)
+		*post_proc = 2;
+	else if (det_out_op0_cond)
+		*post_proc = 0;
+	else
+		*post_proc = 1;
+
+	/* unsupported options */
+	if (*pre_proc == 4 || *pre_proc == 5)
+		return -EINVAL;
+
+	return 0;
+}
+
 /**
  * Request ASRC pair
  *
@@ -239,8 +278,10 @@  static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
 	u32 inrate, outrate, indiv, outdiv;
 	u32 clk_index[2], div[2];
 	int in, out, channels;
+	int pre_proc, post_proc;
 	struct clk *clk;
 	bool ideal;
+	int ret;
 
 	if (!config) {
 		pair_err("invalid pair config\n");
@@ -289,6 +330,12 @@  static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
 		return -EINVAL;
 	}
 
+	ret = fsl_asrc_sel_proc(inrate, outrate, &pre_proc, &post_proc);
+	if (ret) {
+		pair_err("No supported pre-processing options\n");
+		return ret;
+	}
+
 	/* Validate input and output clock sources */
 	clk_index[IN] = clk_map[IN][config->inclk];
 	clk_index[OUT] = clk_map[OUT][config->outclk];
@@ -380,8 +427,8 @@  static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
 	/* Apply configurations for pre- and post-processing */
 	regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
 			   ASRCFG_PREMODi_MASK(index) |	ASRCFG_POSTMODi_MASK(index),
-			   ASRCFG_PREMOD(index, process_option[in][out][0]) |
-			   ASRCFG_POSTMOD(index, process_option[in][out][1]));
+			   ASRCFG_PREMOD(index, pre_proc) |
+			   ASRCFG_POSTMOD(index, post_proc));
 
 	return fsl_asrc_set_ideal_ratio(pair, inrate, outrate);
 }