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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id z20sm58261328pgf.70.2019.04.13.01.28.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 13 Apr 2019 01:28:14 -0700 (PDT) From: Andrey Smirnov To: linux-pm@vger.kernel.org Cc: Andrey Smirnov , Chris Healy , Lucas Stach , Eduardo Valentin , Daniel Lezcano , Angus Ainslie , linux-imx@nxp.com, linux-kernel@vger.kernel.org Subject: [PATCH v4 08/12] thermal: qoriq: Convert driver to use regmap API Date: Sat, 13 Apr 2019 01:27:44 -0700 Message-Id: <20190413082748.29990-9-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190413082748.29990-1-andrew.smirnov@gmail.com> References: <20190413082748.29990-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Convert driver to use regmap API, drop custom LE/BE IO helpers and simplify bit manipulation using regmap_update_bits(). This also allows us to convert some register initialization to use loops and adds convenient debug access to TMU registers via debugfs. Signed-off-by: Andrey Smirnov Cc: Chris Healy Cc: Lucas Stach Cc: Eduardo Valentin Cc: Daniel Lezcano Cc: Angus Ainslie (Purism) Cc: linux-imx@nxp.com Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Daniel Lezcano --- drivers/thermal/qoriq_thermal.c | 159 +++++++++++++++----------------- 1 file changed, 74 insertions(+), 85 deletions(-) diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c index 64cad6d4c1d7..9774323a17bf 100644 --- a/drivers/thermal/qoriq_thermal.c +++ b/drivers/thermal/qoriq_thermal.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "thermal_core.h" @@ -17,75 +18,37 @@ /* * QorIQ TMU Registers */ -struct qoriq_tmu_site_regs { - u32 tritsr; /* Immediate Temperature Site Register */ - u32 tratsr; /* Average Temperature Site Register */ - u8 res0[0x8]; -}; -struct qoriq_tmu_regs { - u32 tmr; /* Mode Register */ +#define REGS_TMR 0x000 /* Mode Register */ #define TMR_DISABLE 0x0 #define TMR_ME 0x80000000 #define TMR_ALPF 0x0c000000 - u32 tsr; /* Status Register */ - u32 tmtmir; /* Temperature measurement interval Register */ + +#define REGS_TMTMIR 0x008 /* Temperature measurement interval Register */ #define TMTMIR_DEFAULT 0x0000000f - u8 res0[0x14]; - u32 tier; /* Interrupt Enable Register */ + +#define REGS_TIER 0x020 /* Interrupt Enable Register */ #define TIER_DISABLE 0x0 - u32 tidr; /* Interrupt Detect Register */ - u32 tiscr; /* Interrupt Site Capture Register */ - u32 ticscr; /* Interrupt Critical Site Capture Register */ - u8 res1[0x10]; - u32 tmhtcrh; /* High Temperature Capture Register */ - u32 tmhtcrl; /* Low Temperature Capture Register */ - u8 res2[0x8]; - u32 tmhtitr; /* High Temperature Immediate Threshold */ - u32 tmhtatr; /* High Temperature Average Threshold */ - u32 tmhtactr; /* High Temperature Average Crit Threshold */ - u8 res3[0x24]; - u32 ttcfgr; /* Temperature Configuration Register */ - u32 tscfgr; /* Sensor Configuration Register */ - u8 res4[0x78]; - struct qoriq_tmu_site_regs site[SITES_MAX]; - u8 res5[0x9f8]; - u32 ipbrr0; /* IP Block Revision Register 0 */ - u32 ipbrr1; /* IP Block Revision Register 1 */ - u8 res6[0x310]; - u32 ttr0cr; /* Temperature Range 0 Control Register */ - u32 ttr1cr; /* Temperature Range 1 Control Register */ - u32 ttr2cr; /* Temperature Range 2 Control Register */ - u32 ttr3cr; /* Temperature Range 3 Control Register */ -}; +#define REGS_TTCFGR 0x080 /* Temperature Configuration Register */ +#define REGS_TSCFGR 0x084 /* Sensor Configuration Register */ + +#define REGS_TRITSR(n) (0x100 + 16 * (n)) /* Immediate Temperature + * Site Register + */ +#define REGS_TTRnCR(n) (0xf10 + 4 * (n)) /* Temperature Range n + * Control Register + */ struct qoriq_tmu_data { - struct qoriq_tmu_regs __iomem *regs; - bool little_endian; + struct regmap *regmap; }; -static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem *addr) -{ - if (p->little_endian) - iowrite32(val, addr); - else - iowrite32be(val, addr); -} - -static u32 tmu_read(struct qoriq_tmu_data *p, void __iomem *addr) -{ - if (p->little_endian) - return ioread32(addr); - else - return ioread32be(addr); -} - static int tmu_get_temp(int id, void *p, int *temp) { struct qoriq_tmu_data *qdata = p; u32 val; - val = tmu_read(qdata, &qdata->regs->site[id].tritsr); + regmap_read(qdata->regmap, REGS_TRITSR(id), &val); *temp = (val & 0xff) * 1000; return 0; @@ -117,7 +80,8 @@ static int qoriq_tmu_register_tmu_zone(struct device *dev, /* Enable monitoring */ if (sites != 0) - tmu_write(qdata, sites | TMR_ME | TMR_ALPF, &qdata->regs->tmr); + regmap_write(qdata->regmap, REGS_TMR, + sites | TMR_ME | TMR_ALPF); return 0; } @@ -136,10 +100,8 @@ static int qoriq_tmu_calibration(struct device *dev, } /* Init temperature range registers */ - tmu_write(data, range[0], &data->regs->ttr0cr); - tmu_write(data, range[1], &data->regs->ttr1cr); - tmu_write(data, range[2], &data->regs->ttr2cr); - tmu_write(data, range[3], &data->regs->ttr3cr); + for (i = 0; i < ARRAY_SIZE(range); i++) + regmap_write(data->regmap, REGS_TTRnCR(i), range[i]); calibration = of_get_property(np, "fsl,tmu-calibration", &len); if (calibration == NULL || len % 8) { @@ -149,9 +111,9 @@ static int qoriq_tmu_calibration(struct device *dev, for (i = 0; i < len; i += 8, calibration += 2) { val = of_read_number(calibration, 1); - tmu_write(data, val, &data->regs->ttcfgr); + regmap_write(data->regmap, REGS_TTCFGR, val); val = of_read_number(calibration + 1, 1); - tmu_write(data, val, &data->regs->tscfgr); + regmap_write(data->regmap, REGS_TSCFGR, val); } return 0; @@ -160,15 +122,32 @@ static int qoriq_tmu_calibration(struct device *dev, static void qoriq_tmu_init_device(struct qoriq_tmu_data *data) { /* Disable interrupt, using polling instead */ - tmu_write(data, TIER_DISABLE, &data->regs->tier); + regmap_write(data->regmap, REGS_TIER, TIER_DISABLE); /* Set update_interval */ - tmu_write(data, TMTMIR_DEFAULT, &data->regs->tmtmir); + regmap_write(data->regmap, REGS_TMTMIR, TMTMIR_DEFAULT); /* Disable monitoring */ - tmu_write(data, TMR_DISABLE, &data->regs->tmr); + regmap_write(data->regmap, REGS_TMR, TMR_DISABLE); } +static const struct regmap_range qoriq_yes_ranges[] = { + regmap_reg_range(REGS_TMR, REGS_TSCFGR), + regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(3)), + /* Read only registers below */ + regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)), +}; + +static const struct regmap_access_table qoriq_wr_table = { + .yes_ranges = qoriq_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges) - 1, +}; + +static const struct regmap_access_table qoriq_rd_table = { + .yes_ranges = qoriq_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges), +}; + static int qoriq_tmu_probe(struct platform_device *pdev) { int ret; @@ -176,26 +155,44 @@ static int qoriq_tmu_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct device *dev = &pdev->dev; struct resource *io; + const bool little_endian = of_property_read_bool(np, "little-endian"); + const enum regmap_endian format_endian = + little_endian ? REGMAP_ENDIAN_LITTLE : REGMAP_ENDIAN_BIG; + const struct regmap_config regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .rd_table = &qoriq_rd_table, + .wr_table = &qoriq_wr_table, + .val_format_endian = format_endian, + .max_register = SZ_4K, + }; + void __iomem *base; data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data), GFP_KERNEL); if (!data) return -ENOMEM; - data->little_endian = of_property_read_bool(np, "little-endian"); - io = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!io) { dev_err(dev, "Failed to get memory region\n"); return -ENODEV; } - data->regs = devm_ioremap(dev, io->start, resource_size(io)); - if (!data->regs) { + base = devm_ioremap(dev, io->start, resource_size(io)); + if (!base) { dev_err(dev, "Failed to get memory region\n"); return -ENODEV; } + data->regmap = devm_regmap_init_mmio(dev, base, ®map_config); + if (IS_ERR(data->regmap)) { + ret = PTR_ERR(data->regmap); + dev_err(dev, "Failed to init regmap (%d)\n", ret); + return ret; + } + qoriq_tmu_init_device(data); /* TMU initialization */ ret = qoriq_tmu_calibration(dev, data); /* TMU calibration */ @@ -218,7 +215,7 @@ static int qoriq_tmu_remove(struct platform_device *pdev) struct qoriq_tmu_data *data = platform_get_drvdata(pdev); /* Disable monitoring */ - tmu_write(data, TMR_DISABLE, &data->regs->tmr); + regmap_write(data->regmap, REGS_TMR, TMR_DISABLE); platform_set_drvdata(pdev, NULL); @@ -226,30 +223,22 @@ static int qoriq_tmu_remove(struct platform_device *pdev) } #ifdef CONFIG_PM_SLEEP -static int qoriq_tmu_suspend(struct device *dev) + +static int qoriq_tmu_suspend_resume(struct device *dev, unsigned int val) { - u32 tmr; struct qoriq_tmu_data *data = dev_get_drvdata(dev); - /* Disable monitoring */ - tmr = tmu_read(data, &data->regs->tmr); - tmr &= ~TMR_ME; - tmu_write(data, tmr, &data->regs->tmr); + return regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, val); +} - return 0; +static int qoriq_tmu_suspend(struct device *dev) +{ + return qoriq_tmu_suspend_resume(dev, 0); } static int qoriq_tmu_resume(struct device *dev) { - u32 tmr; - struct qoriq_tmu_data *data = dev_get_drvdata(dev); - - /* Enable monitoring */ - tmr = tmu_read(data, &data->regs->tmr); - tmr |= TMR_ME; - tmu_write(data, tmr, &data->regs->tmr); - - return 0; + return qoriq_tmu_suspend_resume(dev, TMR_ME); } #endif