[2/4] drm/v3d: Set the correct DMA mask according to the MMU's limits.
diff mbox series

Message ID 20190419001014.23579-2-eric@anholt.net
State New
Headers show
Series
  • [1/4] drm/v3d: Fix debugfs reads of MMU regs.
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Commit Message

Eric Anholt April 19, 2019, 12:10 a.m. UTC
On 7278, we've got 40 bits to work with.

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/v3d/v3d_debugfs.c | 1 +
 drivers/gpu/drm/v3d/v3d_drv.c     | 6 +++++-
 drivers/gpu/drm/v3d/v3d_regs.h    | 8 ++++++++
 3 files changed, 14 insertions(+), 1 deletion(-)

Comments

Paul Kocialkowski April 19, 2019, 8:47 a.m. UTC | #1
Hi,

On Thu, 2019-04-18 at 17:10 -0700, Eric Anholt wrote:
> On 7278, we've got 40 bits to work with.

Although I don't have docs to check, looks sane:

Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>

Cheers,

Paul

> Signed-off-by: Eric Anholt <eric@anholt.net>
> ---
>  drivers/gpu/drm/v3d/v3d_debugfs.c | 1 +
>  drivers/gpu/drm/v3d/v3d_drv.c     | 6 +++++-
>  drivers/gpu/drm/v3d/v3d_regs.h    | 8 ++++++++
>  3 files changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/v3d/v3d_debugfs.c b/drivers/gpu/drm/v3d/v3d_debugfs.c
> index 356a8acfa72d..ab652a034959 100644
> --- a/drivers/gpu/drm/v3d/v3d_debugfs.c
> +++ b/drivers/gpu/drm/v3d/v3d_debugfs.c
> @@ -30,6 +30,7 @@ static const struct v3d_reg_def v3d_hub_reg_defs[] = {
>  	REGDEF(V3D_MMU_CTL),
>  	REGDEF(V3D_MMU_VIO_ADDR),
>  	REGDEF(V3D_MMU_VIO_ID),
> +	REGDEF(V3D_MMU_DEBUG_INFO),
>  };
>  
>  static const struct v3d_reg_def v3d_gca_reg_defs[] = {
> diff --git a/drivers/gpu/drm/v3d/v3d_drv.c b/drivers/gpu/drm/v3d/v3d_drv.c
> index f8d1d2569c1f..7ab36192e6bc 100644
> --- a/drivers/gpu/drm/v3d/v3d_drv.c
> +++ b/drivers/gpu/drm/v3d/v3d_drv.c
> @@ -472,9 +472,9 @@ static int v3d_platform_drm_probe(struct platform_device *pdev)
>  	struct drm_device *drm;
>  	struct v3d_dev *v3d;
>  	int ret;
> +	u32 mmu_debug;
>  	u32 ident1;
>  
> -	dev->coherent_dma_mask = DMA_BIT_MASK(36);
>  
>  	v3d = kzalloc(sizeof(*v3d), GFP_KERNEL);
>  	if (!v3d)
> @@ -491,6 +491,10 @@ static int v3d_platform_drm_probe(struct platform_device *pdev)
>  	if (ret)
>  		goto dev_free;
>  
> +	mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
> +	dev->coherent_dma_mask =
> +		DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
> +
>  	ident1 = V3D_READ(V3D_HUB_IDENT1);
>  	v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
>  		    V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
> diff --git a/drivers/gpu/drm/v3d/v3d_regs.h b/drivers/gpu/drm/v3d/v3d_regs.h
> index 9a8ff0ce648e..54c8c4320da0 100644
> --- a/drivers/gpu/drm/v3d/v3d_regs.h
> +++ b/drivers/gpu/drm/v3d/v3d_regs.h
> @@ -191,6 +191,14 @@
>  /* Address that faulted */
>  #define V3D_MMU_VIO_ADDR                               0x01234
>  
> +#define V3D_MMU_DEBUG_INFO                             0x01238
> +# define V3D_MMU_PA_WIDTH_MASK                         V3D_MASK(11, 8)
> +# define V3D_MMU_PA_WIDTH_SHIFT                        8
> +# define V3D_MMU_VA_WIDTH_MASK                         V3D_MASK(7, 4)
> +# define V3D_MMU_VA_WIDTH_SHIFT                        4
> +# define V3D_MMU_VERSION_MASK                          V3D_MASK(3, 0)
> +# define V3D_MMU_VERSION_SHIFT                         0
> +
>  /* Per-V3D-core registers */
>  
>  #define V3D_CTL_IDENT0                                 0x00000

Patch
diff mbox series

diff --git a/drivers/gpu/drm/v3d/v3d_debugfs.c b/drivers/gpu/drm/v3d/v3d_debugfs.c
index 356a8acfa72d..ab652a034959 100644
--- a/drivers/gpu/drm/v3d/v3d_debugfs.c
+++ b/drivers/gpu/drm/v3d/v3d_debugfs.c
@@ -30,6 +30,7 @@  static const struct v3d_reg_def v3d_hub_reg_defs[] = {
 	REGDEF(V3D_MMU_CTL),
 	REGDEF(V3D_MMU_VIO_ADDR),
 	REGDEF(V3D_MMU_VIO_ID),
+	REGDEF(V3D_MMU_DEBUG_INFO),
 };
 
 static const struct v3d_reg_def v3d_gca_reg_defs[] = {
diff --git a/drivers/gpu/drm/v3d/v3d_drv.c b/drivers/gpu/drm/v3d/v3d_drv.c
index f8d1d2569c1f..7ab36192e6bc 100644
--- a/drivers/gpu/drm/v3d/v3d_drv.c
+++ b/drivers/gpu/drm/v3d/v3d_drv.c
@@ -472,9 +472,9 @@  static int v3d_platform_drm_probe(struct platform_device *pdev)
 	struct drm_device *drm;
 	struct v3d_dev *v3d;
 	int ret;
+	u32 mmu_debug;
 	u32 ident1;
 
-	dev->coherent_dma_mask = DMA_BIT_MASK(36);
 
 	v3d = kzalloc(sizeof(*v3d), GFP_KERNEL);
 	if (!v3d)
@@ -491,6 +491,10 @@  static int v3d_platform_drm_probe(struct platform_device *pdev)
 	if (ret)
 		goto dev_free;
 
+	mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
+	dev->coherent_dma_mask =
+		DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
+
 	ident1 = V3D_READ(V3D_HUB_IDENT1);
 	v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
 		    V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
diff --git a/drivers/gpu/drm/v3d/v3d_regs.h b/drivers/gpu/drm/v3d/v3d_regs.h
index 9a8ff0ce648e..54c8c4320da0 100644
--- a/drivers/gpu/drm/v3d/v3d_regs.h
+++ b/drivers/gpu/drm/v3d/v3d_regs.h
@@ -191,6 +191,14 @@ 
 /* Address that faulted */
 #define V3D_MMU_VIO_ADDR                               0x01234
 
+#define V3D_MMU_DEBUG_INFO                             0x01238
+# define V3D_MMU_PA_WIDTH_MASK                         V3D_MASK(11, 8)
+# define V3D_MMU_PA_WIDTH_SHIFT                        8
+# define V3D_MMU_VA_WIDTH_MASK                         V3D_MASK(7, 4)
+# define V3D_MMU_VA_WIDTH_SHIFT                        4
+# define V3D_MMU_VERSION_MASK                          V3D_MASK(3, 0)
+# define V3D_MMU_VERSION_SHIFT                         0
+
 /* Per-V3D-core registers */
 
 #define V3D_CTL_IDENT0                                 0x00000