| Message ID | 20190424052004.6270-8-vidyas@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Tegra194 PCIe support | expand |
On Wed, Apr 24, 2019 at 10:49:55AM +0530, Vidya Sagar wrote: > Add support to enable CDM (Configuration Dependent Module) registers check > for any data corruption. CDM registers include standard PCIe configuration > space registers, Port Logic registers and iATU and DMA registers. > Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook > Version 4.90a > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > Changes since [v4]: > * None > > Changes since [v3]: > * None > > Changes since [v2]: > * Changed flag name from 'cdm-check' to 'enable-cdm-check' > * Added info about Port Logic and DMA registers being part of CDM > > Changes since [v1]: > * This is a new patch in v2 series > > Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt > index 5561a1c060d0..85b872c42a9f 100644 > --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt > @@ -34,6 +34,11 @@ Optional properties: > - clock-names: Must include the following entries: > - "pcie" > - "pcie_bus" > +- enable-cdm-check: This is a boolean property and if present enables This needs a vendor prefix. > + automatic checking of CDM (Configuration Dependent Module) registers > + for data corruption. CDM registers include standard PCIe configuration > + space registers, Port Logic registers, DMA and iATU (internal Address > + Translation Unit) registers. > RC mode: > - num-viewport: number of view ports configured in hardware. If a platform > does not specify it, the driver assumes 2. > -- > 2.17.1 >
On 4/26/2019 8:02 PM, Rob Herring wrote: > On Wed, Apr 24, 2019 at 10:49:55AM +0530, Vidya Sagar wrote: >> Add support to enable CDM (Configuration Dependent Module) registers check >> for any data corruption. CDM registers include standard PCIe configuration >> space registers, Port Logic registers and iATU and DMA registers. >> Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook >> Version 4.90a >> >> Signed-off-by: Vidya Sagar <vidyas@nvidia.com> >> --- >> Changes since [v4]: >> * None >> >> Changes since [v3]: >> * None >> >> Changes since [v2]: >> * Changed flag name from 'cdm-check' to 'enable-cdm-check' >> * Added info about Port Logic and DMA registers being part of CDM >> >> Changes since [v1]: >> * This is a new patch in v2 series >> >> Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt >> index 5561a1c060d0..85b872c42a9f 100644 >> --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt >> +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt >> @@ -34,6 +34,11 @@ Optional properties: >> - clock-names: Must include the following entries: >> - "pcie" >> - "pcie_bus" >> +- enable-cdm-check: This is a boolean property and if present enables > > This needs a vendor prefix. Why only for this? Since this whole file is for Synopsys DesignWare core based PCIe IP, I thought there is specific prefix required. Am I wrong? Also, CDM checking is a feature of IP and DWC based implementations can choose either to enable this feature at hardware level or not. And whoever enabled it at hardware level (like Tegra194) can set this flag to enable corresponding software support. > >> + automatic checking of CDM (Configuration Dependent Module) registers >> + for data corruption. CDM registers include standard PCIe configuration >> + space registers, Port Logic registers, DMA and iATU (internal Address >> + Translation Unit) registers. >> RC mode: >> - num-viewport: number of view ports configured in hardware. If a platform >> does not specify it, the driver assumes 2. >> -- >> 2.17.1 >>
On Tue, May 7, 2019 at 3:25 AM Vidya Sagar <vidyas@nvidia.com> wrote: > > On 4/26/2019 8:02 PM, Rob Herring wrote: > > On Wed, Apr 24, 2019 at 10:49:55AM +0530, Vidya Sagar wrote: > >> Add support to enable CDM (Configuration Dependent Module) registers check > >> for any data corruption. CDM registers include standard PCIe configuration > >> space registers, Port Logic registers and iATU and DMA registers. > >> Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook > >> Version 4.90a > >> > >> Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > >> --- > >> Changes since [v4]: > >> * None > >> > >> Changes since [v3]: > >> * None > >> > >> Changes since [v2]: > >> * Changed flag name from 'cdm-check' to 'enable-cdm-check' > >> * Added info about Port Logic and DMA registers being part of CDM > >> > >> Changes since [v1]: > >> * This is a new patch in v2 series > >> > >> Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++ > >> 1 file changed, 5 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt > >> index 5561a1c060d0..85b872c42a9f 100644 > >> --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt > >> +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt > >> @@ -34,6 +34,11 @@ Optional properties: > >> - clock-names: Must include the following entries: > >> - "pcie" > >> - "pcie_bus" > >> +- enable-cdm-check: This is a boolean property and if present enables > > > > This needs a vendor prefix. > Why only for this? Since this whole file is for Synopsys DesignWare core based PCIe IP, > I thought there is specific prefix required. Am I wrong? Also, CDM checking is a feature > of IP and DWC based implementations can choose either to enable this feature at hardware level > or not. And whoever enabled it at hardware level (like Tegra194) can set this flag to > enable corresponding software support. TBC, I meant a Synopsys vendor prefix, not NVIDIA. Any property that's not from a common binding should have a vendor prefix. That hasn't always happened, so we do have lots of examples without. Rob
On 5/13/2019 8:45 PM, Rob Herring wrote: > On Tue, May 7, 2019 at 3:25 AM Vidya Sagar <vidyas@nvidia.com> wrote: >> >> On 4/26/2019 8:02 PM, Rob Herring wrote: >>> On Wed, Apr 24, 2019 at 10:49:55AM +0530, Vidya Sagar wrote: >>>> Add support to enable CDM (Configuration Dependent Module) registers check >>>> for any data corruption. CDM registers include standard PCIe configuration >>>> space registers, Port Logic registers and iATU and DMA registers. >>>> Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook >>>> Version 4.90a >>>> >>>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com> >>>> --- >>>> Changes since [v4]: >>>> * None >>>> >>>> Changes since [v3]: >>>> * None >>>> >>>> Changes since [v2]: >>>> * Changed flag name from 'cdm-check' to 'enable-cdm-check' >>>> * Added info about Port Logic and DMA registers being part of CDM >>>> >>>> Changes since [v1]: >>>> * This is a new patch in v2 series >>>> >>>> Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++ >>>> 1 file changed, 5 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt >>>> index 5561a1c060d0..85b872c42a9f 100644 >>>> --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt >>>> +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt >>>> @@ -34,6 +34,11 @@ Optional properties: >>>> - clock-names: Must include the following entries: >>>> - "pcie" >>>> - "pcie_bus" >>>> +- enable-cdm-check: This is a boolean property and if present enables >>> >>> This needs a vendor prefix. >> Why only for this? Since this whole file is for Synopsys DesignWare core based PCIe IP, >> I thought there is specific prefix required. Am I wrong? Also, CDM checking is a feature >> of IP and DWC based implementations can choose either to enable this feature at hardware level >> or not. And whoever enabled it at hardware level (like Tegra194) can set this flag to >> enable corresponding software support. > > TBC, I meant a Synopsys vendor prefix, not NVIDIA. > > Any property that's not from a common binding should have a vendor > prefix. That hasn't always happened, so we do have lots of examples > without. Ok. got it. I'm going to take care of this in V7 series. > > Rob >
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index 5561a1c060d0..85b872c42a9f 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -34,6 +34,11 @@ Optional properties: - clock-names: Must include the following entries: - "pcie" - "pcie_bus" +- enable-cdm-check: This is a boolean property and if present enables + automatic checking of CDM (Configuration Dependent Module) registers + for data corruption. CDM registers include standard PCIe configuration + space registers, Port Logic registers, DMA and iATU (internal Address + Translation Unit) registers. RC mode: - num-viewport: number of view ports configured in hardware. If a platform does not specify it, the driver assumes 2.
Add support to enable CDM (Configuration Dependent Module) registers check for any data corruption. CDM registers include standard PCIe configuration space registers, Port Logic registers and iATU and DMA registers. Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook Version 4.90a Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- Changes since [v4]: * None Changes since [v3]: * None Changes since [v2]: * Changed flag name from 'cdm-check' to 'enable-cdm-check' * Added info about Port Logic and DMA registers being part of CDM Changes since [v1]: * This is a new patch in v2 series Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++ 1 file changed, 5 insertions(+)