diff mbox series

[v2,1/2] arm64: dts: mt8183: Add reset-cells in infracfg

Message ID 1556262618-14281-1-git-send-email-yong.liang@mediatek.com (mailing list archive)
State New, archived
Headers show
Series [v2,1/2] arm64: dts: mt8183: Add reset-cells in infracfg | expand

Commit Message

Yong Liang April 26, 2019, 7:10 a.m. UTC 
From: "yong.liang" <yong.liang@mediatek.com>

Include mt8183-resets.h and add reset-cells in infracfg
in dtsi file.

Signed-off-by: yong.liang <yong.liang@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi |    2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 08274bf..2589e94 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -8,6 +8,7 @@ 
 #include <dt-bindings/clock/mt8183-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/reset-controller/mt8183-resets.h>
 
 / {
 	compatible = "mediatek,mt8183";
@@ -194,6 +195,7 @@ 
 			compatible = "mediatek,mt8183-infracfg", "syscon";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		apmixedsys: syscon@1000c000 {