| Message ID | 1556274165-31022-1-git-send-email-andrew.cooper3@citrix.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | x86/cpu: Use cpu_has_sep for configuring the SYSENTER MSRs | expand |
>>> On 26.04.19 at 12:22, <andrew.cooper3@citrix.com> wrote: > Currently, configuration of the SYSENTER MSRs are behind a vendor check for > Intel and Centaur, but this misses Zhaoxin. > > Use the feature bit, rather than a vendor check. cpu_has_sep is cleared early > for AMD processors, which can't use SYSENTER/SYSEXIT when operating in long > mode. > > Suggested-by: Jan Beulich <JBeulich@suse.com> > Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
diff --git a/xen/arch/x86/acpi/suspend.c b/xen/arch/x86/acpi/suspend.c index 9e69bf2..ba9d2e1 100644 --- a/xen/arch/x86/acpi/suspend.c +++ b/xen/arch/x86/acpi/suspend.c @@ -27,11 +27,13 @@ void save_rest_processor_state(void) rdmsrl(MSR_SHADOW_GS_BASE, saved_kernel_gs_base); rdmsrl(MSR_CSTAR, saved_cstar); rdmsrl(MSR_LSTAR, saved_lstar); - if ( boot_cpu_data.x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR) ) + + if ( cpu_has_sep ) { rdmsrl(MSR_IA32_SYSENTER_ESP, saved_sysenter_esp); rdmsrl(MSR_IA32_SYSENTER_EIP, saved_sysenter_eip); } + if ( cpu_has_xsave ) saved_xcr0 = get_xcr0(); } @@ -51,7 +53,7 @@ void restore_rest_processor_state(void) wrgsbase(saved_gs_base); wrmsrl(MSR_SHADOW_GS_BASE, saved_kernel_gs_base); - if ( boot_cpu_data.x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR) ) + if ( cpu_has_sep ) { /* Recover sysenter MSRs */ wrmsrl(MSR_IA32_SYSENTER_ESP, saved_sysenter_esp); diff --git a/xen/arch/x86/x86_64/traps.c b/xen/arch/x86/x86_64/traps.c index 44af765..cb4bf0a 100644 --- a/xen/arch/x86/x86_64/traps.c +++ b/xen/arch/x86/x86_64/traps.c @@ -334,7 +334,7 @@ void subarch_percpu_traps_init(void) (unsigned long)lstar_enter); stub_va += offset; - if ( boot_cpu_data.x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR) ) + if ( cpu_has_sep ) { /* SYSENTER entry. */ wrmsrl(MSR_IA32_SYSENTER_ESP, stack_bottom);
Currently, configuration of the SYSENTER MSRs are behind a vendor check for Intel and Centaur, but this misses Zhaoxin. Use the feature bit, rather than a vendor check. cpu_has_sep is cleared early for AMD processors, which can't use SYSENTER/SYSEXIT when operating in long mode. Suggested-by: Jan Beulich <JBeulich@suse.com> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> --- CC: Jan Beulich <JBeulich@suse.com> CC: Wei Liu <wei.liu2@citrix.com> CC: Roger Pau Monné <roger.pau@citrix.com> CC: FionaLi-oc <fionali-oc@zhaoxin.com> Please double check that this works for Zhaoxin. I've tried Intel and AMD. --- xen/arch/x86/acpi/suspend.c | 6 ++++-- xen/arch/x86/x86_64/traps.c | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-)