| Message ID | 20190429204314.21220-1-dinguyen@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM: dts: arria10: Add EMAC OCP reset property | expand |
Hi,
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.0.10, v4.19.37, v4.14.114, v4.9.171, v4.4.179, v3.18.139.
v5.0.10: Failed to apply! Possible dependencies:
37f7453a4b7a ("ARM: dts: socfpga: update missing reset property peripherals")
v4.19.37: Failed to apply! Possible dependencies:
0ffc5df823dd ("ARM: dts: socfpga: update NAND clocking for c5/a5")
12b2982a1f72 ("ARM: dts: arria10: update NAND clocking")
37f7453a4b7a ("ARM: dts: socfpga: update missing reset property peripherals")
v4.14.114: Failed to apply! Possible dependencies:
0ffc5df823dd ("ARM: dts: socfpga: update NAND clocking for c5/a5")
12b2982a1f72 ("ARM: dts: arria10: update NAND clocking")
37f7453a4b7a ("ARM: dts: socfpga: update missing reset property peripherals")
84f95684d950 ("ARM: dts: Add SPI0 node for Arria10")
v4.9.171: Failed to apply! Possible dependencies:
0ffc5df823dd ("ARM: dts: socfpga: update NAND clocking for c5/a5")
12b2982a1f72 ("ARM: dts: arria10: update NAND clocking")
1df99da8953a ("ARM: dts: socfpga: Enable QSPI in Arria10 devkit")
37f7453a4b7a ("ARM: dts: socfpga: update missing reset property peripherals")
4eda9b766b04 ("ARM: dts: socfpga: Fix NAND controller clock supply")
5d662bf15dcb ("ARM: dts: socfpga: Add QSPI node for the Arria10")
84f95684d950 ("ARM: dts: Add SPI0 node for Arria10")
c6deff00b904 ("ARM: dts: socfpga: add qspi node")
cda1ade6a25c ("ARM: dts: Add EMAC AXI settings for Arria10")
d837a80d1950 ("ARM: dts: socfpga: add nand controller nodes")
f2d6f8f81781 ("ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip")
f549af06e9b6 ("ARM: dts: socfpga: Add NAND device tree for Arria10")
v4.4.179: Failed to apply! Possible dependencies:
0ffc5df823dd ("ARM: dts: socfpga: update NAND clocking for c5/a5")
12b2982a1f72 ("ARM: dts: arria10: update NAND clocking")
1df99da8953a ("ARM: dts: socfpga: Enable QSPI in Arria10 devkit")
34a315883f60 ("ARM: socfpga: Add support for DENX MCV SoM and MCVEVK baseboard")
37f7453a4b7a ("ARM: dts: socfpga: update missing reset property peripherals")
4eda9b766b04 ("ARM: dts: socfpga: Fix NAND controller clock supply")
5d662bf15dcb ("ARM: dts: socfpga: Add QSPI node for the Arria10")
64ded09d2939 ("ARM: dts: socfpga: Add Altera Arria10 L2 Cache EDAC devicetree entry")
84f95684d950 ("ARM: dts: Add SPI0 node for Arria10")
91f69147d681 ("ARM: socfpga: dts: Enable MMC support at correct place in the DT")
c6deff00b904 ("ARM: dts: socfpga: add qspi node")
cda1ade6a25c ("ARM: dts: Add EMAC AXI settings for Arria10")
d837a80d1950 ("ARM: dts: socfpga: add nand controller nodes")
dfd35b779d6c ("ARM: socfpga: Repair incorrectly applied MCV patch")
f2d6f8f81781 ("ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip")
f549af06e9b6 ("ARM: dts: socfpga: Add NAND device tree for Arria10")
v3.18.139: Failed to apply! Possible dependencies:
034c4411f5f9 ("ARM: dts: Add initial LS1021A TWR board dts support")
112cadfd4365 ("ARM: socfpga: dts: enable ethernet for Arria10 devkit")
302a5ef29d49 ("ARM: BCM5301X: Add DT for Netgear R6300 V2")
34a315883f60 ("ARM: socfpga: Add support for DENX MCV SoM and MCVEVK baseboard")
37f7453a4b7a ("ARM: dts: socfpga: update missing reset property peripherals")
388c44a379f7 ("Documentation: devicetree: Add Exynos-based boards compatible string")
41de6f981216 ("ARM: dts: Add initial LS1021A QDS board dts support")
475dc86d08de ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
51454eb46c02 ("arm: mmp: Make all the dts file to be compiled by Makefile")
57c0f8c9c453 ("ARM: dts: socfpga: Add support of Terasic DE0 Atlas board")
6855e5b70903 ("ARM: socfpga: dts: Add resets for EMACs on Arria10")
74568da48f69 ("ARM: socfpga: dts: enable UART1 for the debug uart")
8872fc22c267 ("ARM: dts: Enable Broadcom Cygnus SoC")
88c8e4c2648c ("ARM: socfpga: dts: rename socdk board file to socdk_sdmmc")
91f69147d681 ("ARM: socfpga: dts: Enable MMC support at correct place in the DT")
ae2ed35a4000 ("ARM: BCM5301X: Add DT for Asus RT-N18U")
ba2a1d6959ac ("ARM: bcm2835: Add device tree for Raspberry Pi model B+")
be9863cac24b ("ARM: socfpga: dts: Add multicast bins and unicast filter entries")
c01e8cdb7bf5 ("ARM: socfpga: dts: Add tx-fifo-depth and rx-fifo-depth properties")
c9ad7bc5fe3c ("ARM: dts: Enable Broadcom Cygnus SoC")
cb612390e546 ("ARM: dts: Only build dtb if associated Arch and/or SoC is enabled")
cda1ade6a25c ("ARM: dts: Add EMAC AXI settings for Arria10")
dd7733da69f1 ("ARM: BCM5301X: Add DT for Buffalo WZR-600DHP2")
dfd35b779d6c ("ARM: socfpga: Repair incorrectly applied MCV patch")
e0cefb3f79d3 ("ARM: dts: add board dts file for Exynos3250-based Monk board")
e1bf86ace4d2 ("ARM: dts: vf500-colibri: add Colibri VF50 support")
e9f9fe35f894 ("ARM: socfpga: dts: Fix gpio dts entry for the correct clock")
faaf348ef468 ("ARM: dts: Add board dts file for exynos3250-rinato")
How should we proceed with this patch?
--
Thanks,
Sasha
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index ae24599d5829..a6206a0d5763 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -431,8 +431,8 @@ rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; clock-names = "stmmaceth"; - resets = <&rst EMAC0_RESET>; - reset-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -451,8 +451,8 @@ rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; clock-names = "stmmaceth"; - resets = <&rst EMAC1_RESET>; - reset-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -470,8 +470,8 @@ tx-fifo-depth = <4096>; rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; - resets = <&rst EMAC2_RESET>; - clock-names = "stmmaceth"; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + clock-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; };
Add the EMAC's OCP reset property on Arria10. The OCP reset bits are also needed to correctly bring the EMACs out of reset correctly. Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- arch/arm/boot/dts/socfpga_arria10.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)