diff mbox series

[1/2] drm/i915: Move the PIPEMISC write the correct place

Message ID 20190502200607.14504-1-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series [1/2] drm/i915: Move the PIPEMISC write the correct place | expand

Commit Message

Ville Syrjala May 2, 2019, 8:06 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

I fumbled the PIPEMISC write into the wrong place. It only gets
called for fastsets, but since value needs to be updated based on
the set of active planes it needs to be done for all plane updates.
Move it to the correct spot.

The symptoms include SDR planes never showing up if a previous
modeset/fastset left the pipe in HDR mode. This was immediately
obvious when running the kms_plane pixel format tests. Unfortunately
the test didn't realize it was scanning out pure black all the time
and declared success anyway.

Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Fixes: 09b25812db10 ("drm/i915: Enable pipe HDR mode on ICL if only HDR planes are used")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Uma Shankar May 3, 2019, 3:29 p.m. UTC | #1 
>-----Original Message-----
>From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
>Sent: Friday, May 3, 2019 1:36 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma <uma.shankar@intel.com>; Sharma, Shashank
><shashank.sharma@intel.com>
>Subject: [PATCH 1/2] drm/i915: Move the PIPEMISC write the correct place
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>I fumbled the PIPEMISC write into the wrong place. It only gets called for fastsets, but
>since value needs to be updated based on the set of active planes it needs to be done
>for all plane updates.
>Move it to the correct spot.
>
>The symptoms include SDR planes never showing up if a previous modeset/fastset left
>the pipe in HDR mode. This was immediately obvious when running the kms_plane
>pixel format tests. Unfortunately the test didn't realize it was scanning out pure black
>all the time and declared success anyway.

Yeah. SDR Planes will not even be considered for blending and result will be
Black output. 

Looks ok now. 
Reviewed-by: Uma Shankar <uma.shankar@intel.com>


>Cc: Uma Shankar <uma.shankar@intel.com>
>Cc: Shashank Sharma <shashank.sharma@intel.com>
>Fixes: 09b25812db10 ("drm/i915: Enable pipe HDR mode on ICL if only HDR planes are
>used")
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_display.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_display.c
>b/drivers/gpu/drm/i915/intel_display.c
>index dd65d7c521c1..28042a16084d 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -4099,9 +4099,6 @@ static void intel_update_pipe_config(const struct
>intel_crtc_state *old_crtc_sta
> 			ironlake_pfit_disable(old_crtc_state);
> 	}
>
>-	if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
>-		bdw_set_pipemisc(new_crtc_state);
>-
> 	if (INTEL_GEN(dev_priv) >= 11)
> 		icl_set_pipe_chicken(crtc);
> }
>@@ -14156,6 +14153,9 @@ static void intel_begin_crtc_commit(struct
>intel_atomic_state *state,
> 	else if (INTEL_GEN(dev_priv) >= 9)
> 		skl_detach_scalers(new_crtc_state);
>
>+	if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
>+		bdw_set_pipemisc(new_crtc_state);
>+
> out:
> 	if (dev_priv->display.atomic_update_watermarks)
> 		dev_priv->display.atomic_update_watermarks(state,
>--
>2.21.0
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dd65d7c521c1..28042a16084d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4099,9 +4099,6 @@  static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta
 			ironlake_pfit_disable(old_crtc_state);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
-		bdw_set_pipemisc(new_crtc_state);
-
 	if (INTEL_GEN(dev_priv) >= 11)
 		icl_set_pipe_chicken(crtc);
 }
@@ -14156,6 +14153,9 @@  static void intel_begin_crtc_commit(struct intel_atomic_state *state,
 	else if (INTEL_GEN(dev_priv) >= 9)
 		skl_detach_scalers(new_crtc_state);
 
+	if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+		bdw_set_pipemisc(new_crtc_state);
+
 out:
 	if (dev_priv->display.atomic_update_watermarks)
 		dev_priv->display.atomic_update_watermarks(state,