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[kvm-unit-tests] x86: Unmask LVTPC on interrupt

Message ID 20190502174125.8706-1-nadav.amit@gmail.com (mailing list archive)
State New, archived
Headers show
Series [kvm-unit-tests] x86: Unmask LVTPC on interrupt | expand

Commit Message

Nadav Amit May 2, 2019, 5:41 p.m. UTC 
From: Nadav Amit <nadav.amit@gmail.com>

According to the SDM: "When a performance monitoring counters interrupt
is generated, the mask bit for its associated LVT entry is set."

Unmask LVTPC on each interrupt by reprogramming it. As the old value is
known, no need for read-modify-write is needed.

Signed-off-by: Nadav Amit <nadav.amit@gmail.com>
---
 x86/pmu.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Paolo Bonzini May 20, 2019, 2:12 p.m. UTC | #1 
On 02/05/19 19:41, nadav.amit@gmail.com wrote:
> From: Nadav Amit <nadav.amit@gmail.com>
> 
> According to the SDM: "When a performance monitoring counters interrupt
> is generated, the mask bit for its associated LVT entry is set."
> 
> Unmask LVTPC on each interrupt by reprogramming it. As the old value is
> known, no need for read-modify-write is needed.
> 
> Signed-off-by: Nadav Amit <nadav.amit@gmail.com>
> ---
>  x86/pmu.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/x86/pmu.c b/x86/pmu.c
> index f7b3010..6658fe9 100644
> --- a/x86/pmu.c
> +++ b/x86/pmu.c
> @@ -184,6 +184,7 @@ static void start_event(pmu_counter_t *evt)
>  	    wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, ctrl);
>      }
>      global_enable(evt);
> +    apic_write(APIC_LVTPC, PC_VECTOR);
>  }
>  
>  static void stop_event(pmu_counter_t *evt)
> 

Queued, thanks.

Paolo
diff mbox series

Patch

diff --git a/x86/pmu.c b/x86/pmu.c
index f7b3010..6658fe9 100644
--- a/x86/pmu.c
+++ b/x86/pmu.c
@@ -184,6 +184,7 @@  static void start_event(pmu_counter_t *evt)
 	    wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, ctrl);
     }
     global_enable(evt);
+    apic_write(APIC_LVTPC, PC_VECTOR);
 }
 
 static void stop_event(pmu_counter_t *evt)