| Message ID | 20190506210854.24300-1-tony@atomide.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: ti: clkctrl: Fix clkdm_clk handling | expand |
Quoting Tony Lindgren (2019-05-06 14:08:54) > We need to always call clkdm_clk_enable() and clkdm_clk_disable() even > the clkctrl clock(s) enabled for the domain do not have any gate register > bits. Otherwise clockdomains may never get enabled except when devices get > probed with the legacy "ti,hwmods" devicetree property. > > Fixes: 88a172526c32 ("clk: ti: add support for clkctrl clocks") > Signed-off-by: Tony Lindgren <tony@atomide.com> > --- Applied to clk-fixes
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -137,9 +137,6 @@ static int _omap4_clkctrl_clk_enable(struct clk_hw *hw) int ret; union omap4_timeout timeout = { 0 }; - if (!clk->enable_bit) - return 0; - if (clk->clkdm) { ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); if (ret) { @@ -151,6 +148,9 @@ static int _omap4_clkctrl_clk_enable(struct clk_hw *hw) } } + if (!clk->enable_bit) + return 0; + val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); val &= ~OMAP4_MODULEMODE_MASK; @@ -179,7 +179,7 @@ static void _omap4_clkctrl_clk_disable(struct clk_hw *hw) union omap4_timeout timeout = { 0 }; if (!clk->enable_bit) - return; + goto exit; val = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
We need to always call clkdm_clk_enable() and clkdm_clk_disable() even the clkctrl clock(s) enabled for the domain do not have any gate register bits. Otherwise clockdomains may never get enabled except when devices get probed with the legacy "ti,hwmods" devicetree property. Fixes: 88a172526c32 ("clk: ti: add support for clkctrl clocks") Signed-off-by: Tony Lindgren <tony@atomide.com> --- drivers/clk/ti/clkctrl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)