phy: rockchip-dp: Avoid power leak by leaving the PHY power on
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Message ID 20190507234857.81414-1-dianders@chromium.org
State New
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  • phy: rockchip-dp: Avoid power leak by leaving the PHY power on
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Commit Message

Douglas Anderson May 7, 2019, 11:48 p.m. UTC
While testing a newer kernel on rk3288-based Chromebooks I found that
the power draw in suspend was higher on newer kernels compared to the
downstream Chrome OS 3.14 kernel.  Specifically the power of an
rk3288-veyron-jerry board that I tested (as measured by the smart
battery) was ~16 mA on Chrome OS 3.14 and ~21 mA on a newer kernel.

I tracked the regression down to the fact that the "DP PHY" driver
didn't exist in our downstream 3.14.  We relied on the eDP driver to
turn on the clock and relied on the fact that the power for the PHY
was default turned on.

Specifically the thing that caused the power regression was turning
the eDP PHY _off_.  Presumably there is some sort of power leak in the
system and when we turn the PHY off something is leaching power from
something else and causing excessive power draw.

Doing a search through device trees shows that this PHY is only ever
used on rk3288.  Presumably this power leak is present on all
rk3288-SoCs running upstream Linux so let's just whack the driver to
make sure we never turn off power.  We'll still leave the parts that
turn _on_ the power and grab the clock, though.

NOTES:
A) If someone can identify what this power leak is and fix it in some
   other way we can revert this patch.
B) If someone can show that their particular board doesn't have this
   power leak (maybe they have rails hooked up differently?) we can
   perhaps add a device tree property indicating that for some boards
   it's OK to turn this rail off.  I don't want to add this property
   until I know of a board that needs it.

Fixes: fd968973de95 ("phy: Add driver for rockchip Display Port PHY")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---
As far as I know Yakir (the original author) is no longer at Rockchip.
I've added a few other Rockchip people and hopefully one of them can
help direct even if they're not directly responsible.

 drivers/phy/rockchip/phy-rockchip-dp.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

Comments

Douglas Anderson May 17, 2019, 11:57 p.m. UTC | #1
Elaine and Caesar,

On Tue, May 7, 2019 at 4:50 PM Douglas Anderson <dianders@chromium.org> wrote:
>
> While testing a newer kernel on rk3288-based Chromebooks I found that
> the power draw in suspend was higher on newer kernels compared to the
> downstream Chrome OS 3.14 kernel.  Specifically the power of an
> rk3288-veyron-jerry board that I tested (as measured by the smart
> battery) was ~16 mA on Chrome OS 3.14 and ~21 mA on a newer kernel.
>
> I tracked the regression down to the fact that the "DP PHY" driver
> didn't exist in our downstream 3.14.  We relied on the eDP driver to
> turn on the clock and relied on the fact that the power for the PHY
> was default turned on.
>
> Specifically the thing that caused the power regression was turning
> the eDP PHY _off_.  Presumably there is some sort of power leak in the
> system and when we turn the PHY off something is leaching power from
> something else and causing excessive power draw.
>
> Doing a search through device trees shows that this PHY is only ever
> used on rk3288.  Presumably this power leak is present on all
> rk3288-SoCs running upstream Linux so let's just whack the driver to
> make sure we never turn off power.  We'll still leave the parts that
> turn _on_ the power and grab the clock, though.
>
> NOTES:
> A) If someone can identify what this power leak is and fix it in some
>    other way we can revert this patch.
> B) If someone can show that their particular board doesn't have this
>    power leak (maybe they have rails hooked up differently?) we can
>    perhaps add a device tree property indicating that for some boards
>    it's OK to turn this rail off.  I don't want to add this property
>    until I know of a board that needs it.
>
> Fixes: fd968973de95 ("phy: Add driver for rockchip Display Port PHY")
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> ---
> As far as I know Yakir (the original author) is no longer at Rockchip.
> I've added a few other Rockchip people and hopefully one of them can
> help direct even if they're not directly responsible.
>
>  drivers/phy/rockchip/phy-rockchip-dp.c | 11 +++++++----
>  1 file changed, 7 insertions(+), 4 deletions(-)

Can you help direct this to the right person?  ...or should we just
land it and assume it's fine?

-Doug
Heiko Stübner May 18, 2019, 7:51 a.m. UTC | #2
Hi,

Am Samstag, 18. Mai 2019, 01:57:47 CEST schrieb Doug Anderson:
> Elaine and Caesar,
> 
> On Tue, May 7, 2019 at 4:50 PM Douglas Anderson <dianders@chromium.org> wrote:
> >
> > While testing a newer kernel on rk3288-based Chromebooks I found that
> > the power draw in suspend was higher on newer kernels compared to the
> > downstream Chrome OS 3.14 kernel.  Specifically the power of an
> > rk3288-veyron-jerry board that I tested (as measured by the smart
> > battery) was ~16 mA on Chrome OS 3.14 and ~21 mA on a newer kernel.
> >
> > I tracked the regression down to the fact that the "DP PHY" driver
> > didn't exist in our downstream 3.14.  We relied on the eDP driver to
> > turn on the clock and relied on the fact that the power for the PHY
> > was default turned on.
> >
> > Specifically the thing that caused the power regression was turning
> > the eDP PHY _off_.  Presumably there is some sort of power leak in the
> > system and when we turn the PHY off something is leaching power from
> > something else and causing excessive power draw.
> >
> > Doing a search through device trees shows that this PHY is only ever
> > used on rk3288.  Presumably this power leak is present on all
> > rk3288-SoCs running upstream Linux so let's just whack the driver to
> > make sure we never turn off power.  We'll still leave the parts that
> > turn _on_ the power and grab the clock, though.
> >
> > NOTES:
> > A) If someone can identify what this power leak is and fix it in some
> >    other way we can revert this patch.
> > B) If someone can show that their particular board doesn't have this
> >    power leak (maybe they have rails hooked up differently?) we can
> >    perhaps add a device tree property indicating that for some boards
> >    it's OK to turn this rail off.  I don't want to add this property
> >    until I know of a board that needs it.
> >
> > Fixes: fd968973de95 ("phy: Add driver for rockchip Display Port PHY")
> > Signed-off-by: Douglas Anderson <dianders@chromium.org>
> > ---
> > As far as I know Yakir (the original author) is no longer at Rockchip.
> > I've added a few other Rockchip people and hopefully one of them can
> > help direct even if they're not directly responsible.
> >
> >  drivers/phy/rockchip/phy-rockchip-dp.c | 11 +++++++----
> >  1 file changed, 7 insertions(+), 4 deletions(-)
> 
> Can you help direct this to the right person?  ...or should we just
> land it and assume it's fine?

I tink Kishon as phy-maintainer is the correct person to take on this
patch, but maybe he's waiting for the merge-window to be over.


Heiko
Douglas Anderson May 18, 2019, 1:42 p.m. UTC | #3
Hi,

On Sat, May 18, 2019 at 12:51 AM Heiko Stuebner <heiko@sntech.de> wrote:
>
> Hi,
>
> Am Samstag, 18. Mai 2019, 01:57:47 CEST schrieb Doug Anderson:
> > Elaine and Caesar,
> >
> > On Tue, May 7, 2019 at 4:50 PM Douglas Anderson <dianders@chromium.org> wrote:
> > >
> > > While testing a newer kernel on rk3288-based Chromebooks I found that
> > > the power draw in suspend was higher on newer kernels compared to the
> > > downstream Chrome OS 3.14 kernel.  Specifically the power of an
> > > rk3288-veyron-jerry board that I tested (as measured by the smart
> > > battery) was ~16 mA on Chrome OS 3.14 and ~21 mA on a newer kernel.
> > >
> > > I tracked the regression down to the fact that the "DP PHY" driver
> > > didn't exist in our downstream 3.14.  We relied on the eDP driver to
> > > turn on the clock and relied on the fact that the power for the PHY
> > > was default turned on.
> > >
> > > Specifically the thing that caused the power regression was turning
> > > the eDP PHY _off_.  Presumably there is some sort of power leak in the
> > > system and when we turn the PHY off something is leaching power from
> > > something else and causing excessive power draw.
> > >
> > > Doing a search through device trees shows that this PHY is only ever
> > > used on rk3288.  Presumably this power leak is present on all
> > > rk3288-SoCs running upstream Linux so let's just whack the driver to
> > > make sure we never turn off power.  We'll still leave the parts that
> > > turn _on_ the power and grab the clock, though.
> > >
> > > NOTES:
> > > A) If someone can identify what this power leak is and fix it in some
> > >    other way we can revert this patch.
> > > B) If someone can show that their particular board doesn't have this
> > >    power leak (maybe they have rails hooked up differently?) we can
> > >    perhaps add a device tree property indicating that for some boards
> > >    it's OK to turn this rail off.  I don't want to add this property
> > >    until I know of a board that needs it.
> > >
> > > Fixes: fd968973de95 ("phy: Add driver for rockchip Display Port PHY")
> > > Signed-off-by: Douglas Anderson <dianders@chromium.org>
> > > ---
> > > As far as I know Yakir (the original author) is no longer at Rockchip.
> > > I've added a few other Rockchip people and hopefully one of them can
> > > help direct even if they're not directly responsible.
> > >
> > >  drivers/phy/rockchip/phy-rockchip-dp.c | 11 +++++++----
> > >  1 file changed, 7 insertions(+), 4 deletions(-)
> >
> > Can you help direct this to the right person?  ...or should we just
> > land it and assume it's fine?
>
> I tink Kishon as phy-maintainer is the correct person to take on this
> patch, but maybe he's waiting for the merge-window to be over.

Yeah, definitely Kishon should be the one to land.  I was kinda hoping
to get confirmation from the Rockchip guys that this was a good idea
across the board for rk3288 since I can only really test
rk3288-veyron.  They'd have access to the SoC design and could tell
more about what this bit actually does in the SoC.

...in any case, if they don't respond then presumably we'd be good to
land once the merge window is over and Kishon is landing patches
again.

-Doug
Caesar Wang May 20, 2019, 8:04 a.m. UTC | #4
Hi Doug,

For now,  nobody of rockchip is responsible for this driver.
Cc: Nickey, Zain, Hjc


On 5/8/19 7:48 AM, Douglas Anderson wrote:
> While testing a newer kernel on rk3288-based Chromebooks I found that
> the power draw in suspend was higher on newer kernels compared to the
> downstream Chrome OS 3.14 kernel.  Specifically the power of an
> rk3288-veyron-jerry board that I tested (as measured by the smart
> battery) was ~16 mA on Chrome OS 3.14 and ~21 mA on a newer kernel.
>
> I tracked the regression down to the fact that the "DP PHY" driver
> didn't exist in our downstream 3.14.  We relied on the eDP driver to
> turn on the clock and relied on the fact that the power for the PHY
> was default turned on.
>
> Specifically the thing that caused the power regression was turning
> the eDP PHY _off_.  Presumably there is some sort of power leak in the
> system and when we turn the PHY off something is leaching power from
> something else and causing excessive power draw.
>
> Doing a search through device trees shows that this PHY is only ever
> used on rk3288.  Presumably this power leak is present on all
> rk3288-SoCs running upstream Linux so let's just whack the driver to
> make sure we never turn off power.  We'll still leave the parts that
> turn _on_ the power and grab the clock, though.
>
> NOTES:
> A) If someone can identify what this power leak is and fix it in some
>     other way we can revert this patch.
> B) If someone can show that their particular board doesn't have this
>     power leak (maybe they have rails hooked up differently?) we can
>     perhaps add a device tree property indicating that for some boards
>     it's OK to turn this rail off.  I don't want to add this property
>     until I know of a board that needs it.
>
> Fixes: fd968973de95 ("phy: Add driver for rockchip Display Port PHY")
> Signed-off-by: Douglas Anderson <dianders@chromium.org>


Reviewed-by: Caesar Wang <wxt@rock-chips.com>

> ---
> As far as I know Yakir (the original author) is no longer at Rockchip.
> I've added a few other Rockchip people and hopefully one of them can
> help direct even if they're not directly responsible.
>
>   drivers/phy/rockchip/phy-rockchip-dp.c | 11 +++++++----
>   1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-dp.c b/drivers/phy/rockchip/phy-rockchip-dp.c
> index 8b267a746576..10bbcd69d6f5 100644
> --- a/drivers/phy/rockchip/phy-rockchip-dp.c
> +++ b/drivers/phy/rockchip/phy-rockchip-dp.c
> @@ -35,7 +35,7 @@ struct rockchip_dp_phy {
>   static int rockchip_set_phy_state(struct phy *phy, bool enable)
>   {
>   	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> -	int ret;
> +	int ret = 0;
>   
>   	if (enable) {
>   		ret = regmap_write(dp->grf, GRF_SOC_CON12,
> @@ -50,9 +50,12 @@ static int rockchip_set_phy_state(struct phy *phy, bool enable)
>   	} else {
>   		clk_disable_unprepare(dp->phy_24m);
>   
> -		ret = regmap_write(dp->grf, GRF_SOC_CON12,
> -				   GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
> -				   GRF_EDP_PHY_SIDDQ_OFF);
> +		/*
> +		 * Intentionally don't turn SIDDQ off when disabling
> +		 * the PHY.  There is a power leak on rk3288 and
> +		 * suspend power _increases_ by 5 mA if you turn this
> +		 * off.
> +		 */


As described by TRM, The “GRF_EDP_PHY_SIDDQ_OFF” that all circuits are 
power down, all
IO are high-Z. That should make sure the PD_VIO[0] was disabled first, 
no active.
But the rk3288 can't turn pd_vio off at the moment.

[0]
PD_VIO Which clock are device clocks:
              *    clocks        devices
              *    *_IEP        IEP:Image Enhancement Processor
              *    *_ISP        ISP:Image Signal Processing
              *    *_VIP        VIP:Video Input Processor
              *    *_VOP*        VOP:Visual Output Processor
              *    *_RGA        RGA
              *    *_EDP*        EDP
              *    *_LVDS_*    LVDS
              *    *_HDMI        HDMI
              *    *_MIPI_*    MIPI


Thanks,
-Caesar


>   	}
>   
>   	return ret;
Kishon Vijay Abraham I June 3, 2019, 11:20 a.m. UTC | #5
Hi,

On 20/05/19 1:34 PM, Caesar Wang wrote:
> Hi Doug,
> 
> For now,  nobody of rockchip is responsible for this driver.
> Cc: Nickey, Zain, Hjc
> 
> 
> On 5/8/19 7:48 AM, Douglas Anderson wrote:
>> While testing a newer kernel on rk3288-based Chromebooks I found that
>> the power draw in suspend was higher on newer kernels compared to the
>> downstream Chrome OS 3.14 kernel.  Specifically the power of an
>> rk3288-veyron-jerry board that I tested (as measured by the smart
>> battery) was ~16 mA on Chrome OS 3.14 and ~21 mA on a newer kernel.
>>
>> I tracked the regression down to the fact that the "DP PHY" driver
>> didn't exist in our downstream 3.14.  We relied on the eDP driver to
>> turn on the clock and relied on the fact that the power for the PHY
>> was default turned on.
>>
>> Specifically the thing that caused the power regression was turning
>> the eDP PHY _off_.  Presumably there is some sort of power leak in the
>> system and when we turn the PHY off something is leaching power from
>> something else and causing excessive power draw.
>>
>> Doing a search through device trees shows that this PHY is only ever
>> used on rk3288.  Presumably this power leak is present on all
>> rk3288-SoCs running upstream Linux so let's just whack the driver to
>> make sure we never turn off power.  We'll still leave the parts that
>> turn _on_ the power and grab the clock, though.
>>
>> NOTES:
>> A) If someone can identify what this power leak is and fix it in some
>>     other way we can revert this patch.
>> B) If someone can show that their particular board doesn't have this
>>     power leak (maybe they have rails hooked up differently?) we can
>>     perhaps add a device tree property indicating that for some boards
>>     it's OK to turn this rail off.  I don't want to add this property
>>     until I know of a board that needs it.
>>
>> Fixes: fd968973de95 ("phy: Add driver for rockchip Display Port PHY")
>> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> 
> 
> Reviewed-by: Caesar Wang <wxt@rock-chips.com>
> 
>> ---
>> As far as I know Yakir (the original author) is no longer at Rockchip.
>> I've added a few other Rockchip people and hopefully one of them can
>> help direct even if they're not directly responsible.
>>
>>   drivers/phy/rockchip/phy-rockchip-dp.c | 11 +++++++----
>>   1 file changed, 7 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/phy/rockchip/phy-rockchip-dp.c
>> b/drivers/phy/rockchip/phy-rockchip-dp.c
>> index 8b267a746576..10bbcd69d6f5 100644
>> --- a/drivers/phy/rockchip/phy-rockchip-dp.c
>> +++ b/drivers/phy/rockchip/phy-rockchip-dp.c
>> @@ -35,7 +35,7 @@ struct rockchip_dp_phy {
>>   static int rockchip_set_phy_state(struct phy *phy, bool enable)
>>   {
>>       struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
>> -    int ret;
>> +    int ret = 0;
>>         if (enable) {
>>           ret = regmap_write(dp->grf, GRF_SOC_CON12,
>> @@ -50,9 +50,12 @@ static int rockchip_set_phy_state(struct phy *phy, bool
>> enable)
>>       } else {
>>           clk_disable_unprepare(dp->phy_24m);
>>   -        ret = regmap_write(dp->grf, GRF_SOC_CON12,
>> -                   GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
>> -                   GRF_EDP_PHY_SIDDQ_OFF);
>> +        /*
>> +         * Intentionally don't turn SIDDQ off when disabling
>> +         * the PHY.  There is a power leak on rk3288 and
>> +         * suspend power _increases_ by 5 mA if you turn this
>> +         * off.
>> +         */

Can someone in Rockchip try to find the root-cause of the issue? Keeping the
PHY off shouldn't increase power draw.

Thanks
Kishon
Douglas Anderson June 3, 2019, 3:22 p.m. UTC | #6
Kishon,

On Mon, Jun 3, 2019 at 4:22 AM Kishon Vijay Abraham I <kishon@ti.com> wrote:
>
> Hi,
>
> On 20/05/19 1:34 PM, Caesar Wang wrote:
> > Hi Doug,
> >
> > For now,  nobody of rockchip is responsible for this driver.
> > Cc: Nickey, Zain, Hjc
> >
> >
> > On 5/8/19 7:48 AM, Douglas Anderson wrote:
> >> While testing a newer kernel on rk3288-based Chromebooks I found that
> >> the power draw in suspend was higher on newer kernels compared to the
> >> downstream Chrome OS 3.14 kernel.  Specifically the power of an
> >> rk3288-veyron-jerry board that I tested (as measured by the smart
> >> battery) was ~16 mA on Chrome OS 3.14 and ~21 mA on a newer kernel.
> >>
> >> I tracked the regression down to the fact that the "DP PHY" driver
> >> didn't exist in our downstream 3.14.  We relied on the eDP driver to
> >> turn on the clock and relied on the fact that the power for the PHY
> >> was default turned on.
> >>
> >> Specifically the thing that caused the power regression was turning
> >> the eDP PHY _off_.  Presumably there is some sort of power leak in the
> >> system and when we turn the PHY off something is leaching power from
> >> something else and causing excessive power draw.
> >>
> >> Doing a search through device trees shows that this PHY is only ever
> >> used on rk3288.  Presumably this power leak is present on all
> >> rk3288-SoCs running upstream Linux so let's just whack the driver to
> >> make sure we never turn off power.  We'll still leave the parts that
> >> turn _on_ the power and grab the clock, though.
> >>
> >> NOTES:
> >> A) If someone can identify what this power leak is and fix it in some
> >>     other way we can revert this patch.
> >> B) If someone can show that their particular board doesn't have this
> >>     power leak (maybe they have rails hooked up differently?) we can
> >>     perhaps add a device tree property indicating that for some boards
> >>     it's OK to turn this rail off.  I don't want to add this property
> >>     until I know of a board that needs it.
> >>
> >> Fixes: fd968973de95 ("phy: Add driver for rockchip Display Port PHY")
> >> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> >
> >
> > Reviewed-by: Caesar Wang <wxt@rock-chips.com>
> >
> >> ---
> >> As far as I know Yakir (the original author) is no longer at Rockchip.
> >> I've added a few other Rockchip people and hopefully one of them can
> >> help direct even if they're not directly responsible.
> >>
> >>   drivers/phy/rockchip/phy-rockchip-dp.c | 11 +++++++----
> >>   1 file changed, 7 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/phy/rockchip/phy-rockchip-dp.c
> >> b/drivers/phy/rockchip/phy-rockchip-dp.c
> >> index 8b267a746576..10bbcd69d6f5 100644
> >> --- a/drivers/phy/rockchip/phy-rockchip-dp.c
> >> +++ b/drivers/phy/rockchip/phy-rockchip-dp.c
> >> @@ -35,7 +35,7 @@ struct rockchip_dp_phy {
> >>   static int rockchip_set_phy_state(struct phy *phy, bool enable)
> >>   {
> >>       struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> >> -    int ret;
> >> +    int ret = 0;
> >>         if (enable) {
> >>           ret = regmap_write(dp->grf, GRF_SOC_CON12,
> >> @@ -50,9 +50,12 @@ static int rockchip_set_phy_state(struct phy *phy, bool
> >> enable)
> >>       } else {
> >>           clk_disable_unprepare(dp->phy_24m);
> >>   -        ret = regmap_write(dp->grf, GRF_SOC_CON12,
> >> -                   GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
> >> -                   GRF_EDP_PHY_SIDDQ_OFF);
> >> +        /*
> >> +         * Intentionally don't turn SIDDQ off when disabling
> >> +         * the PHY.  There is a power leak on rk3288 and
> >> +         * suspend power _increases_ by 5 mA if you turn this
> >> +         * off.
> >> +         */
>
> Can someone in Rockchip try to find the root-cause of the issue? Keeping the
> PHY off shouldn't increase power draw.

It sounded like Chris already answered this, though?  Basically things
aren't hooked up in a way that this line can be turned safely turned
off in rk3288 with the current state of the world.  Chris says that
there's an ordering problem where we've got to turn off PD_VIO
_before_ we turn off SIDDQ.  ...but PD_VIO is a power domain that
contains much more than just eDP.  So if we truly wanted to try to
solve this we'd need to come up with a way to make sure PD_VIO got all
the way off and then turn this off only afterwards.

...and right now on rk3288 it looks like we never actually turn off
PD_VIO while the system is running.

-Doug
Douglas Anderson June 3, 2019, 3:23 p.m. UTC | #7
Hi,

On Mon, Jun 3, 2019 at 8:22 AM Doug Anderson <dianders@chromium.org> wrote:
> > Can someone in Rockchip try to find the root-cause of the issue? Keeping the
> > PHY off shouldn't increase power draw.
>
> It sounded like Chris already answered this, though?  Basically things

Doh!  Don't know why I said Chris when it was clearly Caesar that
answered.  Sorry Caesar!

-Doug
Douglas Anderson July 22, 2019, 9:52 p.m. UTC | #8
Kishon,

On Mon, Jun 3, 2019 at 8:22 AM Doug Anderson <dianders@chromium.org> wrote:
>
> Kishon,
>
> On Mon, Jun 3, 2019 at 4:22 AM Kishon Vijay Abraham I <kishon@ti.com> wrote:
> >
> > Hi,
> >
> > On 20/05/19 1:34 PM, Caesar Wang wrote:
> > > Hi Doug,
> > >
> > > For now,  nobody of rockchip is responsible for this driver.
> > > Cc: Nickey, Zain, Hjc
> > >
> > >
> > > On 5/8/19 7:48 AM, Douglas Anderson wrote:
> > >> While testing a newer kernel on rk3288-based Chromebooks I found that
> > >> the power draw in suspend was higher on newer kernels compared to the
> > >> downstream Chrome OS 3.14 kernel.  Specifically the power of an
> > >> rk3288-veyron-jerry board that I tested (as measured by the smart
> > >> battery) was ~16 mA on Chrome OS 3.14 and ~21 mA on a newer kernel.
> > >>
> > >> I tracked the regression down to the fact that the "DP PHY" driver
> > >> didn't exist in our downstream 3.14.  We relied on the eDP driver to
> > >> turn on the clock and relied on the fact that the power for the PHY
> > >> was default turned on.
> > >>
> > >> Specifically the thing that caused the power regression was turning
> > >> the eDP PHY _off_.  Presumably there is some sort of power leak in the
> > >> system and when we turn the PHY off something is leaching power from
> > >> something else and causing excessive power draw.
> > >>
> > >> Doing a search through device trees shows that this PHY is only ever
> > >> used on rk3288.  Presumably this power leak is present on all
> > >> rk3288-SoCs running upstream Linux so let's just whack the driver to
> > >> make sure we never turn off power.  We'll still leave the parts that
> > >> turn _on_ the power and grab the clock, though.
> > >>
> > >> NOTES:
> > >> A) If someone can identify what this power leak is and fix it in some
> > >>     other way we can revert this patch.
> > >> B) If someone can show that their particular board doesn't have this
> > >>     power leak (maybe they have rails hooked up differently?) we can
> > >>     perhaps add a device tree property indicating that for some boards
> > >>     it's OK to turn this rail off.  I don't want to add this property
> > >>     until I know of a board that needs it.
> > >>
> > >> Fixes: fd968973de95 ("phy: Add driver for rockchip Display Port PHY")
> > >> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> > >
> > >
> > > Reviewed-by: Caesar Wang <wxt@rock-chips.com>
> > >
> > >> ---
> > >> As far as I know Yakir (the original author) is no longer at Rockchip.
> > >> I've added a few other Rockchip people and hopefully one of them can
> > >> help direct even if they're not directly responsible.
> > >>
> > >>   drivers/phy/rockchip/phy-rockchip-dp.c | 11 +++++++----
> > >>   1 file changed, 7 insertions(+), 4 deletions(-)
> > >>
> > >> diff --git a/drivers/phy/rockchip/phy-rockchip-dp.c
> > >> b/drivers/phy/rockchip/phy-rockchip-dp.c
> > >> index 8b267a746576..10bbcd69d6f5 100644
> > >> --- a/drivers/phy/rockchip/phy-rockchip-dp.c
> > >> +++ b/drivers/phy/rockchip/phy-rockchip-dp.c
> > >> @@ -35,7 +35,7 @@ struct rockchip_dp_phy {
> > >>   static int rockchip_set_phy_state(struct phy *phy, bool enable)
> > >>   {
> > >>       struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> > >> -    int ret;
> > >> +    int ret = 0;
> > >>         if (enable) {
> > >>           ret = regmap_write(dp->grf, GRF_SOC_CON12,
> > >> @@ -50,9 +50,12 @@ static int rockchip_set_phy_state(struct phy *phy, bool
> > >> enable)
> > >>       } else {
> > >>           clk_disable_unprepare(dp->phy_24m);
> > >>   -        ret = regmap_write(dp->grf, GRF_SOC_CON12,
> > >> -                   GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
> > >> -                   GRF_EDP_PHY_SIDDQ_OFF);
> > >> +        /*
> > >> +         * Intentionally don't turn SIDDQ off when disabling
> > >> +         * the PHY.  There is a power leak on rk3288 and
> > >> +         * suspend power _increases_ by 5 mA if you turn this
> > >> +         * off.
> > >> +         */
> >
> > Can someone in Rockchip try to find the root-cause of the issue? Keeping the
> > PHY off shouldn't increase power draw.
>
> It sounded like Caesar already answered this, though?  Basically things
> aren't hooked up in a way that this line can be turned safely turned
> off in rk3288 with the current state of the world.  Chris says that
> there's an ordering problem where we've got to turn off PD_VIO
> _before_ we turn off SIDDQ.  ...but PD_VIO is a power domain that
> contains much more than just eDP.  So if we truly wanted to try to
> solve this we'd need to come up with a way to make sure PD_VIO got all
> the way off and then turn this off only afterwards.
>
> ...and right now on rk3288 it looks like we never actually turn off
> PD_VIO while the system is running.

Is now a good time to land this patch since 5.3-rc1 is out?  Do you
need me to re-send?  Hopefully your concerns are all addressed?

-Doug

Patch
diff mbox series

diff --git a/drivers/phy/rockchip/phy-rockchip-dp.c b/drivers/phy/rockchip/phy-rockchip-dp.c
index 8b267a746576..10bbcd69d6f5 100644
--- a/drivers/phy/rockchip/phy-rockchip-dp.c
+++ b/drivers/phy/rockchip/phy-rockchip-dp.c
@@ -35,7 +35,7 @@  struct rockchip_dp_phy {
 static int rockchip_set_phy_state(struct phy *phy, bool enable)
 {
 	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
-	int ret;
+	int ret = 0;
 
 	if (enable) {
 		ret = regmap_write(dp->grf, GRF_SOC_CON12,
@@ -50,9 +50,12 @@  static int rockchip_set_phy_state(struct phy *phy, bool enable)
 	} else {
 		clk_disable_unprepare(dp->phy_24m);
 
-		ret = regmap_write(dp->grf, GRF_SOC_CON12,
-				   GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
-				   GRF_EDP_PHY_SIDDQ_OFF);
+		/*
+		 * Intentionally don't turn SIDDQ off when disabling
+		 * the PHY.  There is a power leak on rk3288 and
+		 * suspend power _increases_ by 5 mA if you turn this
+		 * off.
+		 */
 	}
 
 	return ret;