| Message ID | 5CDBCC89020000780022F1DE@prv1-mh.provo.novell.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | x86emul: add support for missing {, V}PMADDWD insns | expand |
On 15.05.2019 11:23, Jan Beulich wrote: > Their pre-AVX512 incarnations have clearly been overlooked during much > earlier work. Their memory access pattern is entirely standard, so no > specific tests get added to the harness. > > Reported-by: Razvan Cojocaru <rcojocaru@bitdefender.com> > Signed-off-by: Jan Beulich <jbeulich@suse.com> Tested-by: Alexandru Isaila <aisaila@bitdefender.com> > > --- a/xen/arch/x86/x86_emulate/x86_emulate.c > +++ b/xen/arch/x86/x86_emulate/x86_emulate.c > @@ -6624,6 +6624,8 @@ x86_emulate( > case X86EMUL_OPC_VEX_66(0x0f, 0xf3): /* vpsllq xmm/m128,{x,y}mm,{x,y}mm */ > case X86EMUL_OPC_66(0x0f, 0xf4): /* pmuludq xmm/m128,xmm */ > case X86EMUL_OPC_VEX_66(0x0f, 0xf4): /* vpmuludq {x,y}mm/mem,{x,y}mm,{x,y}mm */ > + CASE_SIMD_PACKED_INT(0x0f, 0xf5): /* pmaddwd {,x}mm/mem,{,x}mm */ > + case X86EMUL_OPC_VEX_66(0x0f, 0xf5): /* vpmaddwd {x,y}mm/mem,{x,y}mm,{x,y}mm */ > case X86EMUL_OPC_66(0x0f, 0xf6): /* psadbw xmm/m128,xmm */ > case X86EMUL_OPC_VEX_66(0x0f, 0xf6): /* vpsadbw {x,y}mm/mem,{x,y}mm,{x,y}mm */ > CASE_SIMD_PACKED_INT(0x0f, 0xf8): /* psubb {,x}mm/mem,{,x}mm */ > > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xenproject.org > https://lists.xenproject.org/mailman/listinfo/xen-devel >
On 15/05/2019 09:23, Jan Beulich wrote: > Their pre-AVX512 incarnations have clearly been overlooked during much > earlier work. Their memory access pattern is entirely standard, so no > specific tests get added to the harness. > > Reported-by: Razvan Cojocaru <rcojocaru@bitdefender.com> > Signed-off-by: Jan Beulich <jbeulich@suse.com> > > --- a/xen/arch/x86/x86_emulate/x86_emulate.c > +++ b/xen/arch/x86/x86_emulate/x86_emulate.c > @@ -6624,6 +6624,8 @@ x86_emulate( > case X86EMUL_OPC_VEX_66(0x0f, 0xf3): /* vpsllq xmm/m128,{x,y}mm,{x,y}mm */ > case X86EMUL_OPC_66(0x0f, 0xf4): /* pmuludq xmm/m128,xmm */ > case X86EMUL_OPC_VEX_66(0x0f, 0xf4): /* vpmuludq {x,y}mm/mem,{x,y}mm,{x,y}mm */ > + CASE_SIMD_PACKED_INT(0x0f, 0xf5): /* pmaddwd {,x}mm/mem,{,x}mm */ > + case X86EMUL_OPC_VEX_66(0x0f, 0xf5): /* vpmaddwd {x,y}mm/mem,{x,y}mm,{x,y}mm */ Nothing on this path checks for SSSE3, AFAICT. ~Andrew > case X86EMUL_OPC_66(0x0f, 0xf6): /* psadbw xmm/m128,xmm */ > case X86EMUL_OPC_VEX_66(0x0f, 0xf6): /* vpsadbw {x,y}mm/mem,{x,y}mm,{x,y}mm */ > CASE_SIMD_PACKED_INT(0x0f, 0xf8): /* psubb {,x}mm/mem,{,x}mm */ > >
>>> On 15.05.19 at 12:17, <andrew.cooper3@citrix.com> wrote: > On 15/05/2019 09:23, Jan Beulich wrote: >> --- a/xen/arch/x86/x86_emulate/x86_emulate.c >> +++ b/xen/arch/x86/x86_emulate/x86_emulate.c >> @@ -6624,6 +6624,8 @@ x86_emulate( >> case X86EMUL_OPC_VEX_66(0x0f, 0xf3): /* vpsllq xmm/m128,{x,y}mm,{x,y}mm */ >> case X86EMUL_OPC_66(0x0f, 0xf4): /* pmuludq xmm/m128,xmm */ >> case X86EMUL_OPC_VEX_66(0x0f, 0xf4): /* vpmuludq {x,y}mm/mem,{x,y}mm,{x,y}mm */ >> + CASE_SIMD_PACKED_INT(0x0f, 0xf5): /* pmaddwd {,x}mm/mem,{,x}mm */ >> + case X86EMUL_OPC_VEX_66(0x0f, 0xf5): /* vpmaddwd {x,y}mm/mem,{x,y}mm,{x,y}mm */ > > Nothing on this path checks for SSSE3, AFAICT. Of course not - the insn first got introduced with MMX, then promoted with SSE2 and again with AVX and AVX2. Jan
On 15/05/2019 12:50, Jan Beulich wrote: >>>> On 15.05.19 at 12:17, <andrew.cooper3@citrix.com> wrote: >> On 15/05/2019 09:23, Jan Beulich wrote: >>> --- a/xen/arch/x86/x86_emulate/x86_emulate.c >>> +++ b/xen/arch/x86/x86_emulate/x86_emulate.c >>> @@ -6624,6 +6624,8 @@ x86_emulate( >>> case X86EMUL_OPC_VEX_66(0x0f, 0xf3): /* vpsllq xmm/m128,{x,y}mm,{x,y}mm */ >>> case X86EMUL_OPC_66(0x0f, 0xf4): /* pmuludq xmm/m128,xmm */ >>> case X86EMUL_OPC_VEX_66(0x0f, 0xf4): /* vpmuludq {x,y}mm/mem,{x,y}mm,{x,y}mm */ >>> + CASE_SIMD_PACKED_INT(0x0f, 0xf5): /* pmaddwd {,x}mm/mem,{,x}mm */ >>> + case X86EMUL_OPC_VEX_66(0x0f, 0xf5): /* vpmaddwd {x,y}mm/mem,{x,y}mm,{x,y}mm */ >> Nothing on this path checks for SSSE3, AFAICT. > Of course not - the insn first got introduced with MMX, then > promoted with SSE2 and again with AVX and AVX2. Oh - terribly sorry - I was reading the adjacent instruction in the manual. Sorry for the noise. Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
--- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -6624,6 +6624,8 @@ x86_emulate( case X86EMUL_OPC_VEX_66(0x0f, 0xf3): /* vpsllq xmm/m128,{x,y}mm,{x,y}mm */ case X86EMUL_OPC_66(0x0f, 0xf4): /* pmuludq xmm/m128,xmm */ case X86EMUL_OPC_VEX_66(0x0f, 0xf4): /* vpmuludq {x,y}mm/mem,{x,y}mm,{x,y}mm */ + CASE_SIMD_PACKED_INT(0x0f, 0xf5): /* pmaddwd {,x}mm/mem,{,x}mm */ + case X86EMUL_OPC_VEX_66(0x0f, 0xf5): /* vpmaddwd {x,y}mm/mem,{x,y}mm,{x,y}mm */ case X86EMUL_OPC_66(0x0f, 0xf6): /* psadbw xmm/m128,xmm */ case X86EMUL_OPC_VEX_66(0x0f, 0xf6): /* vpsadbw {x,y}mm/mem,{x,y}mm,{x,y}mm */ CASE_SIMD_PACKED_INT(0x0f, 0xf8): /* psubb {,x}mm/mem,{,x}mm */
Their pre-AVX512 incarnations have clearly been overlooked during much earlier work. Their memory access pattern is entirely standard, so no specific tests get added to the harness. Reported-by: Razvan Cojocaru <rcojocaru@bitdefender.com> Signed-off-by: Jan Beulich <jbeulich@suse.com>