| Message ID | 20190530234014.22340-1-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/ehl: Update MOCS table for EHL | expand |
On Sat, Jun 01, 2019 at 06:22:53AM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/ehl: Update MOCS table for EHL > URL : https://patchwork.freedesktop.org/series/61409/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_6171_full -> Patchwork_13142_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_13142_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_13142_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_13142_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt@kms_cursor_crc@pipe-b-cursor-suspend: > - shard-snb: [PASS][1] -> [DMESG-WARN][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6171/shard-snb1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13142/shard-snb4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html > This seems to be unrelated; some kind of problem reading and then writing to MSR_IA32_ENERGY_PERF_BIAS in the general x86 cpu code during system resume: <4> [748.616267] unchecked MSR access error: RDMSR from 0x1b0 at rIP: 0xffffffff8103391f (intel_epb_restore+0xf/0xa0) <4> [748.616269] Call Trace: <4> [748.616274] syscore_resume+0x5b/0x290 <4> [748.616278] suspend_devices_and_enter+0x977/0xbb0 <4> [748.616285] pm_suspend+0x3e1/0x870 <4> [748.616290] state_store+0x78/0xe0 <4> [748.616296] kernfs_fop_write+0x104/0x190 <4> [748.616302] vfs_write+0xbd/0x1b0 <4> [748.616306] ksys_write+0x8f/0xe0 <4> [748.616311] do_syscall_64+0x55/0x1c0 <4> [748.616315] entry_SYSCALL_64_after_hwframe+0x49/0xbe <4> [748.616318] RIP: 0033:0x7f15ac65c154 <4> [748.616321] Code: 89 02 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 66 90 48 8d 05 b1 07 2e 00 8b 00 85 c0 75 13 b8 01 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 54 f3 c3 66 90 41 54 55 49 89 d4 53 48 89 f5 <4> [748.616323] RSP: 002b:00007ffcf5447988 EFLAGS: 00000246 ORIG_RAX: 0000000000000001 <4> [748.616325] RAX: ffffffffffffffda RBX: 0000000000000004 RCX: 00007f15ac65c154 <4> [748.616327] RDX: 0000000000000004 RSI: 0000564540e265b0 RDI: 000000000000000d <4> [748.616328] RBP: 0000564540e265b0 R08: 0000564540e235e0 R09: 00007f15acb4a540 <4> [748.616330] R10: 0000564540e21010 R11: 0000000000000246 R12: 0000564540e23500 <4> [748.616332] R13: 0000000000000004 R14: 00007f15ac9342a0 R15: 00007f15ac933760 <4> [748.616344] unchecked MSR access error: WRMSR to 0x1b0 (tried to write 0x0000000000000006) at rIP: 0xffffffff81033953 (intel_epb_restore+0x43/0xa0) <4> [748.616345] Call Trace: <4> [748.616348] syscore_resume+0x5b/0x290 <4> [748.616351] suspend_devices_and_enter+0x977/0xbb0 <4> [748.616358] pm_suspend+0x3e1/0x870 <4> [748.616363] state_store+0x78/0xe0 <4> [748.616367] kernfs_fop_write+0x104/0x190 <4> [748.616372] vfs_write+0xbd/0x1b0 <4> [748.616376] ksys_write+0x8f/0xe0 <4> [748.616381] do_syscall_64+0x55/0x1c0 <4> [748.616384] entry_SYSCALL_64_after_hwframe+0x49/0xbe <4> [748.616385] RIP: 0033:0x7f15ac65c154 <4> [748.616387] Code: 89 02 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 66 90 48 8d 05 b1 07 2e 00 8b 00 85 c0 75 13 b8 01 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 54 f3 c3 66 90 41 54 55 49 89 d4 53 48 89 f5 <4> [748.616389] RSP: 002b:00007ffcf5447988 EFLAGS: 00000246 ORIG_RAX: 0000000000000001 <4> [748.616391] RAX: ffffffffffffffda RBX: 0000000000000004 RCX: 00007f15ac65c154 <4> [748.616393] RDX: 0000000000000004 RSI: 0000564540e265b0 RDI: 000000000000000d <4> [748.616394] RBP: 0000564540e265b0 R08: 0000564540e235e0 R09: 00007f15acb4a540 <4> [748.616396] R10: 0000564540e21010 R11: 0000000000000246 R12: 0000564540e23500 <4> [748.616397] R13: 0000000000000004 R14: 00007f15ac9342a0 R15: 00007f15ac933760 This patch only changes gen11 MOCS table, so it shouldn't have any impact on a SNB system. Matt
On Thu, May 30, 2019 at 4:40 PM Matt Roper <matthew.d.roper@intel.com> wrote: > > EHL defines two new MOCS table entries but is otherwise compatible with > the ICL MOCS table. > > These table entries (16 and 17) should still be considered unused for > ICL and as such their behavior remains undefined for that platform. > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_mocs.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c > index 79df66022d3a..1f9db50b1869 100644 > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c > @@ -200,6 +200,14 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { > MOCS_ENTRY(15, \ > LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \ > L3_3_WB), \ > + /* Bypass LLC - Uncached (EHL+) */ \ > + MOCS_ENTRY(16, \ > + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \ > + L3_1_UC), \ > + /* Bypass LLC - L3 (Read-Only) (EHL+) */ \ > + MOCS_ENTRY(17, \ > + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \ > + L3_3_WB), \ > /* Self-Snoop - L3 + LLC */ \ > MOCS_ENTRY(18, \ > LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \ > -- Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Lucas De Marchi > 2.14.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Thu, 2019-05-30 at 16:40 -0700, Matt Roper wrote: > EHL defines two new MOCS table entries but is otherwise compatible > with > the ICL MOCS table. > > These table entries (16 and 17) should still be considered unused for > ICL and as such their behavior remains undefined for that platform. > Requesting another CI round before merging it. Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_mocs.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c > b/drivers/gpu/drm/i915/gt/intel_mocs.c > index 79df66022d3a..1f9db50b1869 100644 > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c > @@ -200,6 +200,14 @@ static const struct drm_i915_mocs_entry > broxton_mocs_table[] = { > MOCS_ENTRY(15, \ > LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \ > L3_3_WB), \ > + /* Bypass LLC - Uncached (EHL+) */ \ > + MOCS_ENTRY(16, \ > + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \ > + L3_1_UC), \ > + /* Bypass LLC - L3 (Read-Only) (EHL+) */ \ > + MOCS_ENTRY(17, \ > + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \ > + L3_3_WB), \ > /* Self-Snoop - L3 + LLC */ \ > MOCS_ENTRY(18, \ > LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \
On Thu, Jun 13, 2019 at 03:27:04PM -0700, Souza, Jose wrote: > On Thu, 2019-05-30 at 16:40 -0700, Matt Roper wrote: > > EHL defines two new MOCS table entries but is otherwise compatible > > with > > the ICL MOCS table. > > > > These table entries (16 and 17) should still be considered unused for > > ICL and as such their behavior remains undefined for that platform. > > > > Requesting another CI round before merging it. > > Reviewed-by: José Roberto de Souza <jose.souza@intel.com> CI re-run looks clean; pushed to dinq. Thanks for the reviews. Matt > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_mocs.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c > > b/drivers/gpu/drm/i915/gt/intel_mocs.c > > index 79df66022d3a..1f9db50b1869 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c > > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c > > @@ -200,6 +200,14 @@ static const struct drm_i915_mocs_entry > > broxton_mocs_table[] = { > > MOCS_ENTRY(15, \ > > LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \ > > L3_3_WB), \ > > + /* Bypass LLC - Uncached (EHL+) */ \ > > + MOCS_ENTRY(16, \ > > + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \ > > + L3_1_UC), \ > > + /* Bypass LLC - L3 (Read-Only) (EHL+) */ \ > > + MOCS_ENTRY(17, \ > > + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \ > > + L3_3_WB), \ > > /* Self-Snoop - L3 + LLC */ \ > > MOCS_ENTRY(18, \ > > LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 79df66022d3a..1f9db50b1869 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -200,6 +200,14 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { MOCS_ENTRY(15, \ LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \ L3_3_WB), \ + /* Bypass LLC - Uncached (EHL+) */ \ + MOCS_ENTRY(16, \ + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \ + L3_1_UC), \ + /* Bypass LLC - L3 (Read-Only) (EHL+) */ \ + MOCS_ENTRY(17, \ + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \ + L3_3_WB), \ /* Self-Snoop - L3 + LLC */ \ MOCS_ENTRY(18, \ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \
EHL defines two new MOCS table entries but is otherwise compatible with the ICL MOCS table. These table entries (16 and 17) should still be considered unused for ICL and as such their behavior remains undefined for that platform. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/intel_mocs.c | 8 ++++++++ 1 file changed, 8 insertions(+)