| Message ID | 1559360354-22974-1-git-send-email-jiaxin.yu@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: add audio node | expand |
On 01/06/2019 05:39, Jiaxin Yu wrote: > Add audio note for MT8183. > Please extend the commit message and the subject line. Subject line should include at least mt8183. > Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> > --- > Hi, > This patch is based on 5.2-rc1 and these patches: > https://patchwork.kernel.org/patch/10962375/ > https://patchwork.kernel.org/patch/10858941/ > > --- > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 93 +++++++++++++++++++++++++++++++- > 1 file changed, 91 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 75c4881..b48194f 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -298,11 +298,100 @@ > clock-names = "baud", "bus"; > status = "disabled"; > }; > - > - audiosys: syscon@11220000 { > + audiosys: audiosys@11220000 { Having a look at the binding descritpion it should be "clock-controller". Regards, Matthias > compatible = "mediatek,mt8183-audiosys", "syscon"; > reg = <0 0x11220000 0 0x1000>; > #clock-cells = <1>; > + afe: mt8183-afe-pcm { > + compatible = "mediatek,mt8183-audio"; > + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; > + power-domains = > + <&scpsys MT8183_POWER_DOMAIN_AUDIO>; > + clocks = <&audiosys CLK_AUDIO_AFE>, > + <&audiosys CLK_AUDIO_DAC>, > + <&audiosys CLK_AUDIO_DAC_PREDIS>, > + <&audiosys CLK_AUDIO_ADC>, > + <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>, > + <&audiosys CLK_AUDIO_22M>, > + <&audiosys CLK_AUDIO_24M>, > + <&audiosys CLK_AUDIO_APLL_TUNER>, > + <&audiosys CLK_AUDIO_APLL2_TUNER>, > + <&audiosys CLK_AUDIO_I2S1>, > + <&audiosys CLK_AUDIO_I2S2>, > + <&audiosys CLK_AUDIO_I2S3>, > + <&audiosys CLK_AUDIO_I2S4>, > + <&audiosys CLK_AUDIO_TDM>, > + <&audiosys CLK_AUDIO_TML>, > + <&infracfg CLK_INFRA_AUDIO>, > + <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, > + <&topckgen CLK_TOP_MUX_AUDIO>, > + <&topckgen CLK_TOP_MUX_AUD_INTBUS>, > + <&topckgen CLK_TOP_SYSPLL_D2_D4>, > + <&topckgen CLK_TOP_MUX_AUD_1>, > + <&topckgen CLK_TOP_APLL1_CK>, > + <&topckgen CLK_TOP_MUX_AUD_2>, > + <&topckgen CLK_TOP_APLL2_CK>, > + <&topckgen CLK_TOP_MUX_AUD_ENG1>, > + <&topckgen CLK_TOP_APLL1_D8>, > + <&topckgen CLK_TOP_MUX_AUD_ENG2>, > + <&topckgen CLK_TOP_APLL2_D8>, > + <&topckgen CLK_TOP_MUX_APLL_I2S0>, > + <&topckgen CLK_TOP_MUX_APLL_I2S1>, > + <&topckgen CLK_TOP_MUX_APLL_I2S2>, > + <&topckgen CLK_TOP_MUX_APLL_I2S3>, > + <&topckgen CLK_TOP_MUX_APLL_I2S4>, > + <&topckgen CLK_TOP_MUX_APLL_I2S5>, > + <&topckgen CLK_TOP_APLL12_DIV0>, > + <&topckgen CLK_TOP_APLL12_DIV1>, > + <&topckgen CLK_TOP_APLL12_DIV2>, > + <&topckgen CLK_TOP_APLL12_DIV3>, > + <&topckgen CLK_TOP_APLL12_DIV4>, > + <&topckgen CLK_TOP_APLL12_DIVB>, > + /*<&topckgen CLK_TOP_APLL12_DIV5>,*/ > + <&clk26m>; > + clock-names = "aud_afe_clk", > + "aud_dac_clk", > + "aud_dac_predis_clk", > + "aud_adc_clk", > + "aud_adc_adda6_clk", > + "aud_apll22m_clk", > + "aud_apll24m_clk", > + "aud_apll1_tuner_clk", > + "aud_apll2_tuner_clk", > + "aud_i2s1_bclk_sw", > + "aud_i2s2_bclk_sw", > + "aud_i2s3_bclk_sw", > + "aud_i2s4_bclk_sw", > + "aud_tdm_clk", > + "aud_tml_clk", > + "aud_infra_clk", > + "mtkaif_26m_clk", > + "top_mux_audio", > + "top_mux_aud_intbus", > + "top_syspll_d2_d4", > + "top_mux_aud_1", > + "top_apll1_ck", > + "top_mux_aud_2", > + "top_apll2_ck", > + "top_mux_aud_eng1", > + "top_apll1_d8", > + "top_mux_aud_eng2", > + "top_apll2_d8", > + "top_i2s0_m_sel", > + "top_i2s1_m_sel", > + "top_i2s2_m_sel", > + "top_i2s3_m_sel", > + "top_i2s4_m_sel", > + "top_i2s5_m_sel", > + "top_apll12_div0", > + "top_apll12_div1", > + "top_apll12_div2", > + "top_apll12_div3", > + "top_apll12_div4", > + "top_apll12_divb", > + /*"top_apll12_div5",*/ > + "top_clk26m_clk"; > + }; > }; > > mfgcfg: syscon@13000000 { >
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 75c4881..b48194f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -298,11 +298,100 @@ clock-names = "baud", "bus"; status = "disabled"; }; - - audiosys: syscon@11220000 { + audiosys: audiosys@11220000 { compatible = "mediatek,mt8183-audiosys", "syscon"; reg = <0 0x11220000 0 0x1000>; #clock-cells = <1>; + afe: mt8183-afe-pcm { + compatible = "mediatek,mt8183-audio"; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; + power-domains = + <&scpsys MT8183_POWER_DOMAIN_AUDIO>; + clocks = <&audiosys CLK_AUDIO_AFE>, + <&audiosys CLK_AUDIO_DAC>, + <&audiosys CLK_AUDIO_DAC_PREDIS>, + <&audiosys CLK_AUDIO_ADC>, + <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>, + <&audiosys CLK_AUDIO_22M>, + <&audiosys CLK_AUDIO_24M>, + <&audiosys CLK_AUDIO_APLL_TUNER>, + <&audiosys CLK_AUDIO_APLL2_TUNER>, + <&audiosys CLK_AUDIO_I2S1>, + <&audiosys CLK_AUDIO_I2S2>, + <&audiosys CLK_AUDIO_I2S3>, + <&audiosys CLK_AUDIO_I2S4>, + <&audiosys CLK_AUDIO_TDM>, + <&audiosys CLK_AUDIO_TML>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, + <&topckgen CLK_TOP_MUX_AUDIO>, + <&topckgen CLK_TOP_MUX_AUD_INTBUS>, + <&topckgen CLK_TOP_SYSPLL_D2_D4>, + <&topckgen CLK_TOP_MUX_AUD_1>, + <&topckgen CLK_TOP_APLL1_CK>, + <&topckgen CLK_TOP_MUX_AUD_2>, + <&topckgen CLK_TOP_APLL2_CK>, + <&topckgen CLK_TOP_MUX_AUD_ENG1>, + <&topckgen CLK_TOP_APLL1_D8>, + <&topckgen CLK_TOP_MUX_AUD_ENG2>, + <&topckgen CLK_TOP_APLL2_D8>, + <&topckgen CLK_TOP_MUX_APLL_I2S0>, + <&topckgen CLK_TOP_MUX_APLL_I2S1>, + <&topckgen CLK_TOP_MUX_APLL_I2S2>, + <&topckgen CLK_TOP_MUX_APLL_I2S3>, + <&topckgen CLK_TOP_MUX_APLL_I2S4>, + <&topckgen CLK_TOP_MUX_APLL_I2S5>, + <&topckgen CLK_TOP_APLL12_DIV0>, + <&topckgen CLK_TOP_APLL12_DIV1>, + <&topckgen CLK_TOP_APLL12_DIV2>, + <&topckgen CLK_TOP_APLL12_DIV3>, + <&topckgen CLK_TOP_APLL12_DIV4>, + <&topckgen CLK_TOP_APLL12_DIVB>, + /*<&topckgen CLK_TOP_APLL12_DIV5>,*/ + <&clk26m>; + clock-names = "aud_afe_clk", + "aud_dac_clk", + "aud_dac_predis_clk", + "aud_adc_clk", + "aud_adc_adda6_clk", + "aud_apll22m_clk", + "aud_apll24m_clk", + "aud_apll1_tuner_clk", + "aud_apll2_tuner_clk", + "aud_i2s1_bclk_sw", + "aud_i2s2_bclk_sw", + "aud_i2s3_bclk_sw", + "aud_i2s4_bclk_sw", + "aud_tdm_clk", + "aud_tml_clk", + "aud_infra_clk", + "mtkaif_26m_clk", + "top_mux_audio", + "top_mux_aud_intbus", + "top_syspll_d2_d4", + "top_mux_aud_1", + "top_apll1_ck", + "top_mux_aud_2", + "top_apll2_ck", + "top_mux_aud_eng1", + "top_apll1_d8", + "top_mux_aud_eng2", + "top_apll2_d8", + "top_i2s0_m_sel", + "top_i2s1_m_sel", + "top_i2s2_m_sel", + "top_i2s3_m_sel", + "top_i2s4_m_sel", + "top_i2s5_m_sel", + "top_apll12_div0", + "top_apll12_div1", + "top_apll12_div2", + "top_apll12_div3", + "top_apll12_div4", + "top_apll12_divb", + /*"top_apll12_div5",*/ + "top_clk26m_clk"; + }; }; mfgcfg: syscon@13000000 {
Add audio note for MT8183. Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> --- Hi, This patch is based on 5.2-rc1 and these patches: https://patchwork.kernel.org/patch/10962375/ https://patchwork.kernel.org/patch/10858941/ --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 93 +++++++++++++++++++++++++++++++- 1 file changed, 91 insertions(+), 2 deletions(-)