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Mon, 03 Jun 2019 10:47:41 -0700 (PDT) From: codekipper@gmail.com To: maxime.ripard@free-electrons.com, wens@csie.org, linux-sunxi@googlegroups.com Date: Mon, 3 Jun 2019 19:47:30 +0200 Message-Id: <20190603174735.21002-5-codekipper@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190603174735.21002-1-codekipper@gmail.com> References: <20190603174735.21002-1-codekipper@gmail.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, Marcus Cooper , lgirdwood@gmail.com, linux-kernel@vger.kernel.org, be17068@iperbole.bo.it, broonie@kernel.org, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH v4 4/9] ASoC: sun4i-i2s: Reduce quirks for sun8i-h3 X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Marcus Cooper We have a number of flags used to identify the functionality of the IP block found on the sun8i-h3 and later devices. As it is only neccessary to identify this new block then replace these flags with just one. Signed-off-by: Marcus Cooper --- sound/soc/sunxi/sun4i-i2s.c | 23 +++++++---------------- 1 file changed, 7 insertions(+), 16 deletions(-) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index e2961d8f6e8c..329883750d6f 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -119,10 +119,7 @@ * * @has_reset: SoC needs reset deasserted. * @has_slave_select_bit: SoC has a bit to enable slave mode. - * @has_fmt_set_lrck_period: SoC requires lrclk period to be set. - * @has_chcfg: tx and rx slot number need to be set. - * @has_chsel_tx_chen: SoC requires that the tx channels are enabled. - * @has_chsel_offset: SoC uses offset for selecting dai operational mode. + * @is_h3_i2s_based: This block is similiar to what is found on the h3. * @reg_offset_txdata: offset of the tx fifo. * @sun4i_i2s_regmap: regmap config to use. * @mclk_offset: Value by which mclkdiv needs to be adjusted. @@ -143,10 +140,7 @@ struct sun4i_i2s_quirks { bool has_reset; bool has_slave_select_bit; - bool has_fmt_set_lrck_period; - bool has_chcfg; - bool has_chsel_tx_chen; - bool has_chsel_offset; + bool is_h3_i2s_based; unsigned int reg_offset_txdata; /* TX FIFO */ const struct regmap_config *sun4i_i2s_regmap; unsigned int mclk_offset; @@ -340,7 +334,7 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, regmap_field_write(i2s->field_clkdiv_mclk_en, 1); /* Set sync period */ - if (i2s->variant->has_fmt_set_lrck_period) + if (i2s->variant->is_h3_i2s_based) regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, SUN8I_I2S_FMT0_LRCK_PERIOD(32)); @@ -366,7 +360,7 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, return -EINVAL; } - if (i2s->variant->has_chcfg) { + if (i2s->variant->is_h3_i2s_based) { regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK, SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels)); @@ -386,7 +380,7 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, regmap_field_write(i2s->field_rxchansel, SUN4I_I2S_CHAN_SEL(params_channels(params))); - if (i2s->variant->has_chsel_tx_chen) + if (i2s->variant->is_h3_i2s_based) regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, SUN8I_I2S_TX_CHAN_EN_MASK, SUN8I_I2S_TX_CHAN_EN(channels)); @@ -449,7 +443,7 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) return -EINVAL; } - if (i2s->variant->has_chsel_offset) { + if (i2s->variant->is_h3_i2s_based) { /* * offset being set indicates that we're connected to an i2s * device, however offset is only used on the sun8i block and @@ -942,10 +936,7 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { .mclk_offset = 1, .bclk_offset = 2, .fmt_offset = 3, - .has_fmt_set_lrck_period = true, - .has_chcfg = true, - .has_chsel_tx_chen = true, - .has_chsel_offset = true, + .is_h3_i2s_based = true, .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8), .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2), .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),