[01/21] drm/i915: Reset only affected engines when handling error capture
diff mbox series

Message ID 20190606093639.9372-2-tvrtko.ursulin@linux.intel.com
State New
Headers show
Series
  • Implicit dev_priv removal
Related show

Commit Message

Tvrtko Ursulin June 6, 2019, 9:36 a.m. UTC
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Pass down the engine mask to i915_clear_error_registers so only affected
engines can be reset on the Gen6/7 path.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_reset.c | 7 ++++---
 drivers/gpu/drm/i915/gt/intel_reset.h | 3 ++-
 drivers/gpu/drm/i915/i915_gem_gtt.c   | 2 +-
 3 files changed, 7 insertions(+), 5 deletions(-)

Comments

Chris Wilson June 6, 2019, 9:44 a.m. UTC | #1
Quoting Tvrtko Ursulin (2019-06-06 10:36:19)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Pass down the engine mask to i915_clear_error_registers so only affected
> engines can be reset on the Gen6/7 path.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

The only downside is that it makes it look more designed.
-Chris
Tvrtko Ursulin June 6, 2019, 9:49 a.m. UTC | #2
On 06/06/2019 10:44, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-06-06 10:36:19)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Pass down the engine mask to i915_clear_error_registers so only affected
>> engines can be reset on the Gen6/7 path.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> 
> The only downside is that it makes it look more designed.

What do you mean?

Regards,

Tvrtko

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 377bc546a68f..7bfb76eb0291 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1160,7 +1160,8 @@  static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
 	intel_uncore_rmw(uncore, reg, 0, 0);
 }
 
-void i915_clear_error_registers(struct drm_i915_private *i915)
+void i915_clear_error_registers(struct drm_i915_private *i915,
+				intel_engine_mask_t engine_mask)
 {
 	struct intel_uncore *uncore = &i915->uncore;
 	u32 eir;
@@ -1193,7 +1194,7 @@  void i915_clear_error_registers(struct drm_i915_private *i915)
 		struct intel_engine_cs *engine;
 		enum intel_engine_id id;
 
-		for_each_engine(engine, i915, id) {
+		for_each_engine_masked(engine, i915, engine_mask, id) {
 			rmw_clear(uncore,
 				  RING_FAULT_REG(engine), RING_FAULT_VALID);
 			intel_uncore_posting_read(uncore,
@@ -1250,7 +1251,7 @@  void i915_handle_error(struct drm_i915_private *i915,
 
 	if (flags & I915_ERROR_CAPTURE) {
 		i915_capture_error_state(i915, engine_mask, msg);
-		i915_clear_error_registers(i915);
+		i915_clear_error_registers(i915, engine_mask);
 	}
 
 	/*
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h
index b52efaab4941..4f3c1acac1a3 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -25,7 +25,8 @@  void i915_handle_error(struct drm_i915_private *i915,
 		       const char *fmt, ...);
 #define I915_ERROR_CAPTURE BIT(0)
 
-void i915_clear_error_registers(struct drm_i915_private *i915);
+void i915_clear_error_registers(struct drm_i915_private *i915,
+				intel_engine_mask_t engine_mask);
 
 void i915_reset(struct drm_i915_private *i915,
 		intel_engine_mask_t stalled_mask,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 56a436858043..5ee3790f2895 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2358,7 +2358,7 @@  void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
 	else
 		return;
 
-	i915_clear_error_registers(dev_priv);
+	i915_clear_error_registers(dev_priv, ALL_ENGINES);
 }
 
 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)