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[5.12.114.167]) by smtp.gmail.com with ESMTPSA id f21sm10385574wmb.2.2019.06.10.05.15.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 Jun 2019 05:15:52 -0700 (PDT) From: Abel Vesa X-Google-Original-From: Abel Vesa To: Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Thomas Gleixner , Marc Zyngier , Lucas Stach , Bai Ping , Lorenzo Pieralisi , Leonard Crestez Subject: [RFC 2/2] arm64: dts: imx8mq: Add idle states and gpcv2 wake_request broken property Date: Mon, 10 Jun 2019 15:13:46 +0300 Message-Id: <20190610121346.15779-3-abel.vesa@nxp.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190610121346.15779-1-abel.vesa@nxp.com> References: <20190610121346.15779-1-abel.vesa@nxp.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190610_051554_307154_20AC9C13 X-CRM114-Status: GOOD ( 12.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Carlo Caione , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add the cpu-sleep idle state with all the necessary parameters and also add the cpu-idle-states to the cpu nodes. The 'broken-wake-request-signals' property is used to let the irq-imx-gpcv2 driver know that the wake request signals from GIC are not linked to the GPC at all and, therefore, the driver should make use of the dedicated workaround to explicitly wake up the target core on every IPI. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index d09b808..7217138 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -103,6 +103,7 @@ #cooling-cells = <2>; nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; + cpu-idle-states = <&CPU_SLEEP>; }; A53_1: cpu@1 { @@ -115,6 +116,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; }; A53_2: cpu@2 { @@ -127,6 +129,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; }; A53_3: cpu@3 { @@ -139,11 +142,27 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; }; A53_L2: l2-cache0 { compatible = "cache"; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + }; a53_opp_table: opp-table { @@ -502,6 +521,7 @@ reg = <0x303a0000 0x10000>; interrupt-parent = <&gic>; interrupt-controller; + broken-wake-request-signals; #interrupt-cells = <3>; pgc {