Message ID | 20190611145135.21399-35-jagan@amarulasolutions.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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bh=Ckb/dVtuw942Plu9XgJ6pHzs/1bm+A1p+7DNE1ADw90=; b=YosfnjWD5VtRKT8H8eG9PpdMKLS3fbBqquDUwOcby6XFSLxe1Cx9lcQPGLxDo+p1Qg p4LMlSx6PGkSZ2QLFwhY9Xu0P0Ve78kyxiZgBk+opgpldzHpHGs3Rz3cXtVtwmUB4PDE JBKOaIw1GqnDyeiUkEXD6kFCNyVtN+x83c860YQs0w/XKjm2Vca48LMlgN2u8mCrLqC8 t/SACDEG+uhtfs6zZGHV1usu9SpBuX00zANhQTtWgf7pp1aI9yGbSMK5wE1MPnu9LpOY sHiladOOPuvMqq0fZjVSfVKaudvhwzrvkkfwsskK4hwqs8gq86vZ3Ugk++s/N096Q+Ie GdWw== X-Gm-Message-State: APjAAAVdWBVp1ndrnpHYBRLr/cVKLmx7fPLrWnh7GVIh+72rS4O313nr /TJASo5lEHuEBW+4RS32wzl9Hw== X-Google-Smtp-Source: APXvYqx6VkHOMAsdNKttuOPOGpRsMDbET+LXthED6rYa89xIpORcS9/+u0D+UP890ROSguwOZKxq6A== X-Received: by 2002:a63:2b8a:: with SMTP id r132mr20451397pgr.196.1560264847320; Tue, 11 Jun 2019 07:54:07 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.18]) by smtp.gmail.com with ESMTPSA id e9sm16206208pfn.154.2019.06.11.07.54.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 07:54:06 -0700 (PDT) From: Jagan Teki <jagan@amarulasolutions.com> To: Simon Glass <sjg@chromium.org>, Philipp Tomsich <philipp.tomsich@theobroma-systems.com>, Kever Yang <kever.yang@rock-chips.com>, YouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de Subject: [PATCH 34/92] ram: rk3399: Add phy pctrl reset support Date: Tue, 11 Jun 2019 20:20:37 +0530 Message-Id: <20190611145135.21399-35-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190611145135.21399-1-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190611_075407_914077_4C53B4C4 X-CRM114-Status: GOOD ( 10.14 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms <linux-rockchip.lists.infradead.org> List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-rockchip>, <mailto:linux-rockchip-request@lists.infradead.org?subject=unsubscribe> List-Archive: <http://lists.infradead.org/pipermail/linux-rockchip/> List-Post: <mailto:linux-rockchip@lists.infradead.org> List-Help: <mailto:linux-rockchip-request@lists.infradead.org?subject=help> List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-rockchip>, <mailto:linux-rockchip-request@lists.infradead.org?subject=subscribe> Cc: linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki <jagan@amarulasolutions.com>, gajjar04akash@gmail.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" <linux-rockchip-bounces@lists.infradead.org> Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP |
Series |
ram: rk3399: Add LPDDR4 support
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expand
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diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index e3945feca3..bbf56f29ae 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -35,6 +35,10 @@ #define PHY_DRV_ODT_40 0xe #define PHY_DRV_ODT_34_3 0xf +#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ + ((n) << (8 + (ch) * 4))) +#define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ + ((n) << (9 + (ch) * 4))) struct chan_info { struct rk3399_ddr_pctl_regs *pctl; struct rk3399_ddr_pi_regs *pi; @@ -79,6 +83,29 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n) } } +static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, + u32 phy) +{ + channel &= 0x1; + ctl &= 0x1; + phy &= 0x1; + writel(CRU_SFTRST_DDR_CTRL(channel, ctl) | + CRU_SFTRST_DDR_PHY(channel, phy), + &cru->softrst_con[4]); +} + +static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel) +{ + rkclk_ddr_reset(cru, channel, 1, 1); + udelay(10); + + rkclk_ddr_reset(cru, channel, 1, 0); + udelay(10); + + rkclk_ddr_reset(cru, channel, 0, 0); + udelay(10); +} + static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs, u32 freq) { @@ -1126,6 +1153,7 @@ static int sdram_init(struct dram_info *dram, { unsigned char dramtype = sdram_params->base.dramtype; unsigned int ddr_freq = sdram_params->base.ddr_freq; + struct rk3399_cru *cru = dram->cru; int channel; int ret; @@ -1142,6 +1170,7 @@ static int sdram_init(struct dram_info *dram, const struct chan_info *chan = &dram->chan[channel]; struct rk3399_ddr_publ_regs *publ = chan->publ; + phy_pctrl_reset(cru, channel); phy_dll_bypass_set(publ, ddr_freq); if (channel >= sdram_params->base.num_channels)