Message ID | 20190611145135.21399-66-jagan@amarulasolutions.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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bh=FkCYBiID/lhz7C8lOWKp6q5hTcm2jkjoqxxR1eSGoWw=; b=U428xLauFH3i3WKawlP8bq21quthj08JfKLIo1QocnRBZN1jgRhpQzhGnwPTWlZXOC qXmRDGQfewZ1RDORvMHfYAwg6A+PjaERobIf/KsIILmjGWW/gnCTHdd3LTl92krJHJGN cSVHa5lFg3j/21xuq7RYHV1kk8wRoORI3L3xnPUV2z2yhORHa8MnsS1nNtdLpgiqIpht 4H9Xi+ndP5uRjHR4D/pOIKRjoK15HEtMNq3fp82RksiszhgrFCMjmUKJLVdyBbtK/QjE EvAwrsOwMk/nUnYyuuff+/Ekv5gRFkrGxUa/Z00+B5j0lNcFYpjkpSyuKICwOguYQHW5 07cA== X-Gm-Message-State: APjAAAUZqQiZNhj+HEFj8WYaU1VPlLPuH5bZOHLcXgmj0tr3nxUlKc32 2fOJX8aS5CaLRYkH3ugFcDE8WQ== X-Google-Smtp-Source: APXvYqyWdQ48lqgM9QENWM5m0E58lqfEmcss3CI6HgprTLdToDRjf2pYqHuCtFesnqqp4UxGIR9q2w== X-Received: by 2002:a63:d415:: with SMTP id a21mr2996509pgh.229.1560264969049; Tue, 11 Jun 2019 07:56:09 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.18]) by smtp.gmail.com with ESMTPSA id e9sm16206208pfn.154.2019.06.11.07.56.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 07:56:08 -0700 (PDT) From: Jagan Teki <jagan@amarulasolutions.com> To: Simon Glass <sjg@chromium.org>, Philipp Tomsich <philipp.tomsich@theobroma-systems.com>, Kever Yang <kever.yang@rock-chips.com>, YouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de Subject: [PATCH 65/92] ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4 Date: Tue, 11 Jun 2019 20:21:08 +0530 Message-Id: <20190611145135.21399-66-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190611145135.21399-1-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190611_075609_702477_896BFCA3 X-CRM114-Status: UNSURE ( 9.14 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms <linux-rockchip.lists.infradead.org> List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-rockchip>, <mailto:linux-rockchip-request@lists.infradead.org?subject=unsubscribe> List-Archive: <http://lists.infradead.org/pipermail/linux-rockchip/> List-Post: <mailto:linux-rockchip@lists.infradead.org> List-Help: <mailto:linux-rockchip-request@lists.infradead.org?subject=help> List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-rockchip>, <mailto:linux-rockchip-request@lists.infradead.org?subject=subscribe> Cc: linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki <jagan@amarulasolutions.com>, gajjar04akash@gmail.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" <linux-rockchip-bounces@lists.infradead.org> Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP |
Series |
ram: rk3399: Add LPDDR4 support
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diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 4328790a4f..78e249e164 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -37,6 +37,8 @@ #define PHY_BOOSTP_EN 0x1 #define PHY_BOOSTN_EN 0x1 +#define PHY_SLEWP_EN 0x1 +#define PHY_SLEWN_EN 0x1 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ ((n) << (8 + (ch) * 4))) @@ -335,6 +337,25 @@ static int phy_io_config(const struct chan_info *chan, clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20); /* PHY_939 PHY_PAD_CS_DRIVE */ clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20); + + /* SLEWP_EN & SLEWN_EN */ + reg_value = ((PHY_SLEWP_EN << 3) | PHY_SLEWN_EN); + /* PHY_924 PHY_PAD_FDBK_DRIVE */ + clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8); + /* PHY_926 PHY_PAD_DATA_DRIVE */ + clrsetbits_le32(&denali_phy[926], 0x3f, reg_value); + /* PHY_927 PHY_PAD_DQS_DRIVE */ + clrsetbits_le32(&denali_phy[927], 0x3f, reg_value); + /* PHY_928 PHY_PAD_ADDR_DRIVE */ + clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8); + /* PHY_929 PHY_PAD_CLK_DRIVE */ + clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8); + /* PHY_935 PHY_PAD_CKE_DRIVE */ + clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8); + /* PHY_937 PHY_PAD_RST_DRIVE */ + clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8); + /* PHY_939 PHY_PAD_CS_DRIVE */ + clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8); } /* speed setting */