[2/2] arm64/mm: show TAINT_CPU_OUT_OF_SPEC warning if the cache size is over the spec.
diff mbox series

Message ID 20190611151731.6135-3-msys.mizuma@gmail.com
State New
Headers show
Series
  • Correct the cache line size warning
Related show

Commit Message

Masayoshi Mizuma June 11, 2019, 3:17 p.m. UTC
From: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>

Show the warning and taints as TAINT_CPU_OUT_OF_SPEC if the cache line
size is greater than the maximum.

Signed-off-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Tested-by: Zhang Lei <zhang.lei@jp.fujitsu.com>
---
 arch/arm64/include/asm/cache.h | 2 ++
 arch/arm64/mm/init.c           | 5 +++++
 2 files changed, 7 insertions(+)

Comments

Catalin Marinas June 11, 2019, 3:41 p.m. UTC | #1
On Tue, Jun 11, 2019 at 11:17:31AM -0400, Masayoshi Mizuma wrote:
> From: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
> 
> Show the warning and taints as TAINT_CPU_OUT_OF_SPEC if the cache line
> size is greater than the maximum.

In general the "out of spec" part is a misnomer, we tend to apply it to
CPU features that are not supported by the kernel rather than some CPU
feature not compliant with the architecture (we call the latter errata).

I suggest you drop this patch.
Masayoshi Mizuma June 11, 2019, 4:18 p.m. UTC | #2
On Tue, Jun 11, 2019 at 04:41:06PM +0100, Catalin Marinas wrote:
> On Tue, Jun 11, 2019 at 11:17:31AM -0400, Masayoshi Mizuma wrote:
> > From: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
> > 
> > Show the warning and taints as TAINT_CPU_OUT_OF_SPEC if the cache line
> > size is greater than the maximum.
> 
> In general the "out of spec" part is a misnomer, we tend to apply it to
> CPU features that are not supported by the kernel rather than some CPU
> feature not compliant with the architecture (we call the latter errata).
> 
> I suggest you drop this patch.

Thank you for your comments. I agree with you, so I drop this
patch.

Thanks,
Masa

Patch
diff mbox series

diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index 926434f413fa..636e277fefc9 100644
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h
@@ -91,6 +91,8 @@  static inline u32 cache_type_cwg(void)
 
 #define __read_mostly __attribute__((__section__(".data..read_mostly")))
 
+#define ARM64_MAX_CACHE_LINE_SIZE	2048
+
 static inline int cache_line_size(void)
 {
 	u32 cwg = cache_type_cwg();
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index d2adffb81b5d..df621d90b19c 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -562,6 +562,11 @@  void __init mem_init(void)
 		 */
 		sysctl_overcommit_memory = OVERCOMMIT_ALWAYS;
 	}
+
+	WARN_TAINT(cache_line_size() > ARM64_MAX_CACHE_LINE_SIZE,
+		   TAINT_CPU_OUT_OF_SPEC,
+		   "CTR_EL0.CWG is greater than the spec (%d > %d)",
+		   cache_line_size(), ARM64_MAX_CACHE_LINE_SIZE);
 }
 
 void free_initmem(void)