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Unlike conventional Display pipeline in allwinner, R40 have TCON TCOP which would interact various block like muxes, tcon lcd, tcon_tv for better pipeline fitting. For MIPI DSI pipeline, we have to configure the tcon_lcd0 block which would interact with tcon_top for upper pipeline connections and dsi block for lower pipeline connections. So, this patch created that pipeline by adding new nodes for tcon_lcd0, dsi, dphy and connet them to make proper pipeline fitting. Signed-off-by: Jagan Teki --- arch/arm/boot/dts/sun8i-r40.dtsi | 73 ++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 219d2dca16b3..eb6b2960c700 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -623,6 +623,7 @@ tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { reg = <0>; + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; }; tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { @@ -701,6 +702,45 @@ }; }; + tcon_lcd0: lcd-controller@1c71000 { + compatible = "allwinner,sun8i-r40-tcon-lcd"; + reg = <0x01c71000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON_LCD0>, <&ccu CLK_TCON_LCD0>; + clock-names = "ahb", "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_TCON_LCD0>, <&ccu RST_BUS_LVDS>; + reset-names = "lcd", "lvds"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_lcd0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; + }; + }; + + tcon_lcd0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon_lcd0_out_dsi_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_tcon_lcd0_out>; + }; + }; + }; + }; + tcon_tv0: lcd-controller@1c73000 { compatible = "allwinner,sun8i-r40-tcon-tv"; reg = <0x01c73000 0x1000>; @@ -798,6 +838,39 @@ interrupts = ; }; + dsi: dsi@1ca0000 { + compatible = "allwinner,sun8i-r40-mipi-dsi", + "allwinner,sun50i-a64-mipi-dsi"; + reg = <0x01ca0000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_MIPI_DSI>; + clock-names = "bus"; + resets = <&ccu RST_BUS_MIPI_DSI>; + phys = <&dphy>; + phy-names = "dphy"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + port { + dsi_in_tcon_lcd0_out: endpoint { + remote-endpoint = <&tcon_lcd0_out_dsi_out>; + }; + }; + }; + + dphy: d-phy@1ca1000 { + compatible = "allwinner,sun8i-r40-mipi-dphy", + "allwinner,sun6i-a31-mipi-dphy"; + reg = <0x01ca1000 0x1000>; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&tcon_top CLK_TCON_TOP_DSI>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + status = "disabled"; + #phy-cells = <0>; + }; + hdmi: hdmi@1ee0000 { compatible = "allwinner,sun8i-r40-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi";