diff mbox series

[v2,08/99] ram: rk3399: Clear PI_175 interrupts in data training

Message ID 20190617073252.27810-9-jagan@amarulasolutions.com (mailing list archive)
State New, archived
Headers show
Series ram: rk3399: Add LPDDR4 support | expand

Commit Message

Jagan Teki June 17, 2019, 7:31 a.m. UTC
Clear the PI_175 interrupts before processing actual
data training in all relevant calls.

This would help to clear interrupt from previous training.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
 drivers/ram/rockchip/sdram_rk3399.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Comments

Kever Yang July 15, 2019, 12:39 p.m. UTC | #1
On 2019/6/17 下午3:31, Jagan Teki wrote:
> Clear the PI_175 interrupts before processing actual
> data training in all relevant calls.
>
> This would help to clear interrupt from previous training.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> Signed-off-by: YouMin Chen <cym@rock-chips.com>

Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>

Thanks,
  - Kever
> ---
>   drivers/ram/rockchip/sdram_rk3399.c | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
>
> diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
> index 20a3e89c17..1898466b4c 100644
> --- a/drivers/ram/rockchip/sdram_rk3399.c
> +++ b/drivers/ram/rockchip/sdram_rk3399.c
> @@ -617,6 +617,9 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
>   	u32 obs_0, obs_1, obs_2, obs_err = 0;
>   	u32 rank = params->ch[channel].rank;
>   
> +	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
> +	writel(0x00003f7c, (&denali_pi[175]));
> +
>   	for (i = 0; i < rank; i++) {
>   		select_per_cs_training_index(chan, i);
>   
> @@ -671,6 +674,9 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
>   	u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
>   	u32 rank = params->ch[channel].rank;
>   
> +	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
> +	writel(0x00003f7c, (&denali_pi[175]));
> +
>   	for (i = 0; i < rank; i++) {
>   		select_per_cs_training_index(chan, i);
>   
> @@ -730,6 +736,9 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
>   	u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
>   	u32 rank = params->ch[channel].rank;
>   
> +	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
> +	writel(0x00003f7c, (&denali_pi[175]));
> +
>   	for (i = 0; i < rank; i++) {
>   		select_per_cs_training_index(chan, i);
>   
> @@ -789,6 +798,9 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,
>   	u32 i, tmp;
>   	u32 rank = params->ch[channel].rank;
>   
> +	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
> +	writel(0x00003f7c, (&denali_pi[175]));
> +
>   	for (i = 0; i < rank; i++) {
>   		select_per_cs_training_index(chan, i);
>   
> @@ -834,6 +846,9 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
>   	u32 i, tmp;
>   	u32 rank = params->ch[channel].rank;
>   
> +	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
> +	writel(0x00003f7c, (&denali_pi[175]));
> +
>   	for (i = 0; i < rank; i++) {
>   		select_per_cs_training_index(chan, i);
>
diff mbox series

Patch

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 20a3e89c17..1898466b4c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -617,6 +617,9 @@  static int data_training_ca(const struct chan_info *chan, u32 channel,
 	u32 obs_0, obs_1, obs_2, obs_err = 0;
 	u32 rank = params->ch[channel].rank;
 
+	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+	writel(0x00003f7c, (&denali_pi[175]));
+
 	for (i = 0; i < rank; i++) {
 		select_per_cs_training_index(chan, i);
 
@@ -671,6 +674,9 @@  static int data_training_wl(const struct chan_info *chan, u32 channel,
 	u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
 	u32 rank = params->ch[channel].rank;
 
+	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+	writel(0x00003f7c, (&denali_pi[175]));
+
 	for (i = 0; i < rank; i++) {
 		select_per_cs_training_index(chan, i);
 
@@ -730,6 +736,9 @@  static int data_training_rg(const struct chan_info *chan, u32 channel,
 	u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
 	u32 rank = params->ch[channel].rank;
 
+	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+	writel(0x00003f7c, (&denali_pi[175]));
+
 	for (i = 0; i < rank; i++) {
 		select_per_cs_training_index(chan, i);
 
@@ -789,6 +798,9 @@  static int data_training_rl(const struct chan_info *chan, u32 channel,
 	u32 i, tmp;
 	u32 rank = params->ch[channel].rank;
 
+	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+	writel(0x00003f7c, (&denali_pi[175]));
+
 	for (i = 0; i < rank; i++) {
 		select_per_cs_training_index(chan, i);
 
@@ -834,6 +846,9 @@  static int data_training_wdql(const struct chan_info *chan, u32 channel,
 	u32 i, tmp;
 	u32 rank = params->ch[channel].rank;
 
+	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+	writel(0x00003f7c, (&denali_pi[175]));
+
 	for (i = 0; i < rank; i++) {
 		select_per_cs_training_index(chan, i);