| Message ID | 20190618010108.27499-4-John.C.Harrison@Intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update whitelist support for new hardware | expand |
On 18/06/2019 02:01, John.C.Harrison@Intel.com wrote: > From: John Harrison <John.C.Harrison@Intel.com> > > Updated whitelist table for ICL. > > v2: Reduce changes to just those required for media driver until > the selftest can be updated to support the new features of the > other entries. > > Signed-off-by: John Harrison <John.C.Harrison@Intel.com> > Signed-off-by: Robert M. Fosha <robert.m.fosha@intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 38 +++++++++++++++------ > 1 file changed, 27 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 5308a0864e78..d37ebcddb963 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1113,17 +1113,33 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) > { > struct i915_wa_list *w = &engine->whitelist; > > - if (engine->class != RENDER_CLASS) > - return; > - > - /* WaAllowUMDToModifyHalfSliceChicken7:icl */ > - whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); > - > - /* WaAllowUMDToModifySamplerMode:icl */ > - whitelist_reg(w, GEN10_SAMPLER_MODE); > - > - /* WaEnableStateCacheRedirectToCS:icl */ > - whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); > + switch (engine->class) { > + case RENDER_CLASS: > + /* WaAllowUMDToModifyHalfSliceChicken7:icl */ > + whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); > + > + /* WaAllowUMDToModifySamplerMode:icl */ > + whitelist_reg(w, GEN10_SAMPLER_MODE); > + > + /* WaEnableStateCacheRedirectToCS:icl */ > + whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); > + break; > + > + case VIDEO_DECODE_CLASS: > + /* hucStatusRegOffset */ > + whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), > + RING_FORCE_TO_NONPRIV_RD); > + /* hucUKernelHdrInfoRegOffset */ > + whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), > + RING_FORCE_TO_NONPRIV_RD); > + /* hucStatus2RegOffset */ > + whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), > + RING_FORCE_TO_NONPRIV_RD); > + break; > + > + default: > + break; > + } > } > > void intel_engine_init_whitelist(struct intel_engine_cs *engine) > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 5308a0864e78..d37ebcddb963 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1113,17 +1113,33 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) { struct i915_wa_list *w = &engine->whitelist; - if (engine->class != RENDER_CLASS) - return; - - /* WaAllowUMDToModifyHalfSliceChicken7:icl */ - whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); - - /* WaAllowUMDToModifySamplerMode:icl */ - whitelist_reg(w, GEN10_SAMPLER_MODE); - - /* WaEnableStateCacheRedirectToCS:icl */ - whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); + switch (engine->class) { + case RENDER_CLASS: + /* WaAllowUMDToModifyHalfSliceChicken7:icl */ + whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); + + /* WaAllowUMDToModifySamplerMode:icl */ + whitelist_reg(w, GEN10_SAMPLER_MODE); + + /* WaEnableStateCacheRedirectToCS:icl */ + whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); + break; + + case VIDEO_DECODE_CLASS: + /* hucStatusRegOffset */ + whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), + RING_FORCE_TO_NONPRIV_RD); + /* hucUKernelHdrInfoRegOffset */ + whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), + RING_FORCE_TO_NONPRIV_RD); + /* hucStatus2RegOffset */ + whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), + RING_FORCE_TO_NONPRIV_RD); + break; + + default: + break; + } } void intel_engine_init_whitelist(struct intel_engine_cs *engine)