diff mbox series

arm64/mm: don't initialize pgd_cache twice

Message ID 1560843149-13845-1-git-send-email-rppt@linux.ibm.com (mailing list archive)
State Mainlined, archived
Commit 615c48ad8f4275b4d39fa57df68d4015078be201
Headers show
Series arm64/mm: don't initialize pgd_cache twice | expand

Commit Message

Mike Rapoport June 18, 2019, 7:32 a.m. UTC
When PGD_SIZE != PAGE_SIZE, arm64 uses kmem_cache for allocation of PGD
memory. That cache was initialized twice: first through
pgtable_cache_init() alias and then as an override for weak
pgd_cache_init().

Remove the alias from pgtable_cache_init() and keep the only pgd_cache
initialization in pgd_cache_init().

Fixes: caa841360134 ("x86/mm: Initialize PGD cache during mm initialization")
Signed-off-by: Mike Rapoport <rppt@linux.ibm.com>
---
 arch/arm64/include/asm/pgtable.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

Comments

Will Deacon June 18, 2019, 9:25 a.m. UTC | #1
On Tue, Jun 18, 2019 at 10:32:29AM +0300, Mike Rapoport wrote:
> When PGD_SIZE != PAGE_SIZE, arm64 uses kmem_cache for allocation of PGD
> memory. That cache was initialized twice: first through
> pgtable_cache_init() alias and then as an override for weak
> pgd_cache_init().
> 
> Remove the alias from pgtable_cache_init() and keep the only pgd_cache
> initialization in pgd_cache_init().
> 
> Fixes: caa841360134 ("x86/mm: Initialize PGD cache during mm initialization")
> Signed-off-by: Mike Rapoport <rppt@linux.ibm.com>
> ---
>  arch/arm64/include/asm/pgtable.h | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)

Thanks, Mike.

Will
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 2c41b04..851c68d 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -812,8 +812,7 @@  extern int kern_addr_valid(unsigned long addr);
 
 #include <asm-generic/pgtable.h>
 
-void pgd_cache_init(void);
-#define pgtable_cache_init	pgd_cache_init
+static inline void pgtable_cache_init(void) { }
 
 /*
  * On AArch64, the cache coherency is handled via the set_pte_at() function.