diff mbox series

drm/i915/ehl: Add port_cl_dw10 to combo phy vswing sequence

Message ID 20190621222009.18188-1-clinton.a.taylor@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/ehl: Add port_cl_dw10 to combo phy vswing sequence | expand

Commit Message

Taylor, Clinton A June 21, 2019, 10:20 p.m. UTC 
From: Clint Taylor <clinton.a.taylor@intel.com>

Elkhart Lake has additional bits in port_cl_dw10 that should be set
during vswing programming. According to BSPEC these bits should be set
based on OEM selection. Since VBT does not contain a definition for
these bits we will currently clear them until VBT is updated to give
OEMs the ability to set them.

bspec: 21257
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jose Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
 drivers/gpu/drm/i915/i915_reg.h          | 4 ++++
 2 files changed, 12 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7925a176f900..6bde92a4041a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2430,6 +2430,14 @@  static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
 		level = n_entries - 1;
 	}
 
+	/* set PORT_CL_DW10 */
+	if (IS_ELKHARTLAKE(dev_priv)) {
+		val = I915_READ(ICL_PORT_CL_DW10(port));
+		val &= ~(O_EDP4K2K_MODE_OVRD_EN | O_EDP4K2K_MODE_OVRD_VAL |
+			O_RTERM100EN_H_OVRD_EN | O_RTERM100EN_H_OVRD_VAL);
+		I915_WRITE(ICL_PORT_CL_DW10(port), val);
+	}
+
 	/* Set PORT_TX_DW5 */
 	val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
 	val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e6009cefb18..ce8602442480 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1819,6 +1819,10 @@  enum i915_power_well_id {
 #define  PWR_DOWN_LN_3_1_0		(0xb << 4)
 #define  PWR_DOWN_LN_MASK		(0xf << 4)
 #define  PWR_DOWN_LN_SHIFT		4
+#define  O_EDP4K2K_MODE_OVRD_EN		(1 << 3)
+#define  O_EDP4K2K_MODE_OVRD_VAL	(1 << 2)
+#define  O_RTERM100EN_H_OVRD_EN		(1 << 1)
+#define  O_RTERM100EN_H_OVRD_VAL	(1 << 0)
 
 #define ICL_PORT_CL_DW12(port)		_MMIO(_ICL_PORT_CL_DW(12, port))
 #define   ICL_LANE_ENABLE_AUX		(1 << 0)