From patchwork Thu Jun 27 15:22:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 11019883 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 322F114BB for ; Thu, 27 Jun 2019 15:24:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 216882237D for ; Thu, 27 Jun 2019 15:24:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 15D27289F1; Thu, 27 Jun 2019 15:24:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8F1572237D for ; Thu, 27 Jun 2019 15:24:24 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hgWEc-0004LQ-Kf; Thu, 27 Jun 2019 15:22:50 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hgWEb-0004LB-5R for xen-devel@lists.xenproject.org; Thu, 27 Jun 2019 15:22:49 +0000 X-Inumbo-ID: 69a89ad0-98ef-11e9-a2af-17f79dc87198 Received: from prv1-mh.provo.novell.com (unknown [137.65.248.33]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id 69a89ad0-98ef-11e9-a2af-17f79dc87198; Thu, 27 Jun 2019 15:22:45 +0000 (UTC) Received: from INET-PRV1-MTA by prv1-mh.provo.novell.com with Novell_GroupWise; Thu, 27 Jun 2019 09:22:44 -0600 Message-Id: <5D14DF43020000780023B990@prv1-mh.provo.novell.com> X-Mailer: Novell GroupWise Internet Agent 18.1.1 Date: Thu, 27 Jun 2019 09:22:43 -0600 From: "Jan Beulich" To: "xen-devel" References: <5D024C500200007800237DD8@prv1-mh.provo.novell.com> <5D14DDA6020000780023B96E@prv1-mh.provo.novell.com> In-Reply-To: <5D14DDA6020000780023B96E@prv1-mh.provo.novell.com> Mime-Version: 1.0 Content-Disposition: inline Subject: [Xen-devel] [PATCH v2 08/10] AMD/IOMMU: adjust setup of internal interrupt for x2APIC mode X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Brian Woods , Suravee Suthikulpanit Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP In order to be able to express all possible destinations we need to make use of this non-MSI-capability based mechanism. The new IRQ controller structure can re-use certain MSI functions, though. For now general and PPR interrupts still share a single vector, IRQ, and hence handler. Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper --- a/xen/drivers/passthrough/amd/iommu_init.c +++ b/xen/drivers/passthrough/amd/iommu_init.c @@ -472,6 +472,44 @@ static hw_irq_controller iommu_maskable_ .set_affinity = set_msi_affinity, }; +static void set_x2apic_affinity(struct irq_desc *desc, const cpumask_t *mask) +{ + struct amd_iommu *iommu = desc->action->dev_id; + unsigned int dest = set_desc_affinity(desc, mask); + union amd_iommu_x2apic_control ctrl = {}; + unsigned long flags; + + if ( dest == BAD_APICID ) + return; + + msi_compose_msg(desc->arch.vector, NULL, &iommu->msi.msg); + iommu->msi.msg.dest32 = dest; + + ctrl.dest_mode = MASK_EXTR(iommu->msi.msg.address_lo, + MSI_ADDR_DESTMODE_MASK); + ctrl.int_type = MASK_EXTR(iommu->msi.msg.data, + MSI_DATA_DELIVERY_MODE_MASK); + ctrl.vector = desc->arch.vector; + ctrl.dest_lo = dest; + ctrl.dest_hi = dest >> 24; + + spin_lock_irqsave(&iommu->lock, flags); + writeq(ctrl.raw, iommu->mmio_base + IOMMU_XT_INT_CTRL_MMIO_OFFSET); + writeq(ctrl.raw, iommu->mmio_base + IOMMU_XT_PPR_INT_CTRL_MMIO_OFFSET); + spin_unlock_irqrestore(&iommu->lock, flags); +} + +static hw_irq_controller iommu_x2apic_type = { + .typename = "IOMMU-x2APIC", + .startup = irq_startup_none, + .shutdown = irq_shutdown_none, + .enable = irq_enable_none, + .disable = irq_disable_none, + .ack = ack_nonmaskable_msi_irq, + .end = end_nonmaskable_msi_irq, + .set_affinity = set_x2apic_affinity, +}; + static void parse_event_log_entry(struct amd_iommu *iommu, u32 entry[]) { u16 domain_id, device_id, flags; @@ -726,8 +764,6 @@ static void iommu_interrupt_handler(int static bool_t __init set_iommu_interrupt_handler(struct amd_iommu *iommu) { int irq, ret; - hw_irq_controller *handler; - u16 control; irq = create_irq(NUMA_NO_NODE); if ( irq <= 0 ) @@ -747,20 +783,43 @@ static bool_t __init set_iommu_interrupt PCI_SLOT(iommu->bdf), PCI_FUNC(iommu->bdf)); return 0; } - control = pci_conf_read16(iommu->seg, PCI_BUS(iommu->bdf), - PCI_SLOT(iommu->bdf), PCI_FUNC(iommu->bdf), - iommu->msi.msi_attrib.pos + PCI_MSI_FLAGS); - iommu->msi.msi.nvec = 1; - if ( is_mask_bit_support(control) ) - { - iommu->msi.msi_attrib.maskbit = 1; - iommu->msi.msi.mpos = msi_mask_bits_reg(iommu->msi.msi_attrib.pos, - is_64bit_address(control)); - handler = &iommu_maskable_msi_type; + + if ( iommu->ctrl.int_cap_xt_en ) + { + struct irq_desc *desc = irq_to_desc(irq); + + iommu->msi.msi_attrib.pos = MSI_TYPE_IOMMU; + iommu->msi.msi_attrib.maskbit = 0; + iommu->msi.msi_attrib.is_64 = 1; + + desc->msi_desc = &iommu->msi; + desc->handler = &iommu_x2apic_type; + + ret = 0; } else - handler = &iommu_msi_type; - ret = __setup_msi_irq(irq_to_desc(irq), &iommu->msi, handler); + { + hw_irq_controller *handler; + u16 control; + + control = pci_conf_read16(iommu->seg, PCI_BUS(iommu->bdf), + PCI_SLOT(iommu->bdf), PCI_FUNC(iommu->bdf), + iommu->msi.msi_attrib.pos + PCI_MSI_FLAGS); + + iommu->msi.msi.nvec = 1; + if ( is_mask_bit_support(control) ) + { + iommu->msi.msi_attrib.maskbit = 1; + iommu->msi.msi.mpos = msi_mask_bits_reg(iommu->msi.msi_attrib.pos, + is_64bit_address(control)); + handler = &iommu_maskable_msi_type; + } + else + handler = &iommu_msi_type; + + ret = __setup_msi_irq(irq_to_desc(irq), &iommu->msi, handler); + } + if ( !ret ) ret = request_irq(irq, 0, iommu_interrupt_handler, "amd_iommu", iommu); if ( ret ) @@ -838,8 +897,19 @@ static void enable_iommu(struct amd_iomm struct irq_desc *desc = irq_to_desc(iommu->msi.irq); spin_lock(&desc->lock); - set_msi_affinity(desc, &cpu_online_map); - spin_unlock(&desc->lock); + + if ( iommu->ctrl.int_cap_xt_en ) + { + set_x2apic_affinity(desc, &cpu_online_map); + spin_unlock(&desc->lock); + } + else + { + set_msi_affinity(desc, &cpu_online_map); + spin_unlock(&desc->lock); + + amd_iommu_msi_enable(iommu, IOMMU_CONTROL_ENABLED); + } } amd_iommu_msi_enable(iommu, IOMMU_CONTROL_ENABLED); @@ -879,7 +949,9 @@ static void disable_iommu(struct amd_iom return; } - amd_iommu_msi_enable(iommu, IOMMU_CONTROL_DISABLED); + if ( !iommu->ctrl.int_cap_xt_en ) + amd_iommu_msi_enable(iommu, IOMMU_CONTROL_DISABLED); + set_iommu_command_buffer_control(iommu, IOMMU_CONTROL_DISABLED); set_iommu_event_log_control(iommu, IOMMU_CONTROL_DISABLED); --- a/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h +++ b/xen/include/asm-x86/hvm/svm/amd-iommu-defs.h @@ -416,6 +416,25 @@ union amd_iommu_ext_features { } flds; }; +/* x2APIC Control Registers */ +#define IOMMU_XT_INT_CTRL_MMIO_OFFSET 0x0170 +#define IOMMU_XT_PPR_INT_CTRL_MMIO_OFFSET 0x0178 +#define IOMMU_XT_GA_INT_CTRL_MMIO_OFFSET 0x0180 + +union amd_iommu_x2apic_control { + uint64_t raw; + struct { + unsigned int :2; + unsigned int dest_mode:1; + unsigned int :5; + unsigned int dest_lo:24; + unsigned int vector:8; + unsigned int int_type:1; /* DM in IOMMU spec 3.04 */ + unsigned int :15; + unsigned int dest_hi:8; + }; +}; + /* Status Register*/ #define IOMMU_STATUS_MMIO_OFFSET 0x2020 #define IOMMU_STATUS_EVENT_OVERFLOW_MASK 0x00000001