| Message ID | 20190627103937.3842-1-nadav.amit@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [kvm-unit-tests,v2] x86: Reset lapic after boot | expand |
On 06/27/2019 03:39 AM, Nadav Amit wrote: > Do not assume that the local APIC is in a xAPIC mode after reset. > Instead reset it first, since it might be in x2APIC mode, from which a > transition in xAPIC is invalid. s/transition in/transition to/ > > To use reset_apic(), change it to use xapic_write(), in order to make safe to use > while apic_ops might change concurrently by x2apic_enable(). s/x2apic_enable/enable_x2apic/ > > Cc: Krish Sadhukhan <krish.sadhukhan@oracle.com> > Signed-off-by: Nadav Amit <nadav.amit@gmail.com> > --- > lib/x86/apic.c | 2 +- > x86/cstart64.S | 2 ++ > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/lib/x86/apic.c b/lib/x86/apic.c > index 1514730..b3e39ae 100644 > --- a/lib/x86/apic.c > +++ b/lib/x86/apic.c > @@ -164,7 +164,7 @@ void reset_apic(void) > { > disable_apic(); > wrmsr(MSR_IA32_APICBASE, rdmsr(MSR_IA32_APICBASE) | APIC_EN); > - apic_write(APIC_SPIV, 0x1ff); > + xapic_write(APIC_SPIV, 0x1ff); > } > > u32 ioapic_read_reg(unsigned reg) > diff --git a/x86/cstart64.S b/x86/cstart64.S > index 9791282..1889c6b 100644 > --- a/x86/cstart64.S > +++ b/x86/cstart64.S > @@ -228,6 +228,7 @@ save_id: > retq > > ap_start64: > + call reset_apic > call load_tss > call enable_apic > call save_id > @@ -240,6 +241,7 @@ ap_start64: > jmp 1b > > start64: > + call reset_apic > call load_tss > call mask_pic_interrupts > call enable_apic Except the above minor things, Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
On 27/06/19 12:39, Nadav Amit wrote: > Do not assume that the local APIC is in a xAPIC mode after reset. > Instead reset it first, since it might be in x2APIC mode, from which a > transition in xAPIC is invalid. > > To use reset_apic(), change it to use xapic_write(), in order to make safe to use > while apic_ops might change concurrently by x2apic_enable(). > > Cc: Krish Sadhukhan <krish.sadhukhan@oracle.com> > Signed-off-by: Nadav Amit <nadav.amit@gmail.com> > --- Also needs the 32-bit version: diff --git a/x86/cstart.S b/x86/cstart.S index 2fa4c30..575101b 100644 --- a/x86/cstart.S +++ b/x86/cstart.S @@ -143,6 +143,7 @@ ap_start32: lock/xaddl %esp, smp_stacktop setup_percpu_area call prepare_32 + call reset_apic call save_id call load_tss call enable_apic @@ -155,6 +156,7 @@ ap_start32: jmp 1b start32: + call reset_apic call save_id call load_tss call mask_pic_interrupts Paolo
diff --git a/lib/x86/apic.c b/lib/x86/apic.c index 1514730..b3e39ae 100644 --- a/lib/x86/apic.c +++ b/lib/x86/apic.c @@ -164,7 +164,7 @@ void reset_apic(void) { disable_apic(); wrmsr(MSR_IA32_APICBASE, rdmsr(MSR_IA32_APICBASE) | APIC_EN); - apic_write(APIC_SPIV, 0x1ff); + xapic_write(APIC_SPIV, 0x1ff); } u32 ioapic_read_reg(unsigned reg) diff --git a/x86/cstart64.S b/x86/cstart64.S index 9791282..1889c6b 100644 --- a/x86/cstart64.S +++ b/x86/cstart64.S @@ -228,6 +228,7 @@ save_id: retq ap_start64: + call reset_apic call load_tss call enable_apic call save_id @@ -240,6 +241,7 @@ ap_start64: jmp 1b start64: + call reset_apic call load_tss call mask_pic_interrupts call enable_apic
Do not assume that the local APIC is in a xAPIC mode after reset. Instead reset it first, since it might be in x2APIC mode, from which a transition in xAPIC is invalid. To use reset_apic(), change it to use xapic_write(), in order to make safe to use while apic_ops might change concurrently by x2apic_enable(). Cc: Krish Sadhukhan <krish.sadhukhan@oracle.com> Signed-off-by: Nadav Amit <nadav.amit@gmail.com> --- lib/x86/apic.c | 2 +- x86/cstart64.S | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-)