[RFCv2,3/8] arm64: dts: imx8mm: Add dram dvfs irqs to ccm node
diff mbox series

Message ID a502a0c3be3b6c5c5a04cb982e0fe165cd19ca71.1561707104.git.leonard.crestez@nxp.com
State RFC, archived
Headers show
Series
  • Add imx8mm bus frequency switching
Related show

Commit Message

Leonard Crestez June 28, 2019, 7:39 a.m. UTC
This could probably be avoided by handling these in secure world.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

Patch
diff mbox series

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 232a7412755a..5da905c257ad 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -449,10 +449,18 @@ 
 				#clock-cells = <1>;
 				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
 					 <&clk_ext3>, <&clk_ext4>;
 				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 					      "clk_ext3", "clk_ext4";
+				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-name = "irq_busfreq_0",
+						 "irq_busfreq_1",
+						 "irq_busfreq_2",
+						 "irq_busfreq_3";
 			};
 
 			src: reset-controller@30390000 {
 				compatible = "fsl,imx8mm-src", "syscon";
 				reg = <0x30390000 0x10000>;