[RFCv2,8/8] arm64: dts: imx8mm: Add devfreq-imx nodes
diff mbox series

Message ID f5714b11a0f46b20cef3cad0cf615bc1093499de.1561707104.git.leonard.crestez@nxp.com
State RFC, archived
Headers show
Series
  • Add imx8mm bus frequency switching
Related show

Commit Message

Leonard Crestez June 28, 2019, 7:39 a.m. UTC
The imx8mm has multiple buses which can be scaled with some degree of
independence. Expose them as devfreq devices for userspace scaling.

It shouldn't be possible to get the system in a non-working state this
way. It is primarily aimed at testing and fine performance tuning.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 54 +++++++++++++++++++++++
 1 file changed, 54 insertions(+)

Patch
diff mbox series

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 3b4b112814f7..aa9ed418652d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -121,10 +121,32 @@ 
 			opp-supported-hw = <0x8>, <0x7>;
 			clock-latency-ns = <150000>;
 		};
 	};
 
+	ddrc_opp_table: ddrc-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-25M {
+			opp-hz = /bits/ 64 <25000000>;
+		};
+		opp-750M {
+			opp-hz = /bits/ 64 <750000000>;
+		};
+	};
+
+	noc_opp_table: noc-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-150M {
+			opp-hz = /bits/ 64 <150000000>;
+		};
+		opp-750M {
+			opp-hz = /bits/ 64 <750000000>;
+		};
+	};
+
 	memory@40000000 {
 		device_type = "memory";
 		reg = <0x0 0x40000000 0 0x80000000>;
 	};
 
@@ -748,10 +770,35 @@ 
 				status = "disabled";
 			};
 
 		};
 
+		pl301_main: nic@32000000 {
+			compatible = "fsl,imx8mm-nic";
+			reg = <0x32000000 0x100000>;
+			clocks = <&clk IMX8MM_CLK_MAIN_AXI>;
+		};
+
+		pl301_wakeup: nic@32100000 {
+			compatible = "fsl,imx8mm-nic";
+			reg = <0x32100000 0x100000>;
+			clocks = <&clk IMX8MM_CLK_AHB>;
+		};
+
+		pl301_enet: nic@32400000 {
+			compatible = "fsl,imx8mm-nic";
+			reg = <0x32400000 0x100000>;
+			clocks = <&clk IMX8MM_CLK_ENET_AXI>;
+		};
+
+		noc: noc@32700000 {
+			compatible = "fsl,imx8mm-noc";
+			reg = <0x32700000 0x100000>;
+			clocks = <&clk IMX8MM_CLK_NOC>;
+			operating-points-v2 = <&noc_opp_table>;
+		};
+
 		aips4: bus@32c00000 {
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0x32c00000 0x32c00000 0x400000>;
@@ -835,7 +882,14 @@ 
 			      <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
 			#interrupt-cells = <3>;
 			interrupt-controller;
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		ddrc: dram-controller@3d400000 {
+			compatible = "fsl,imx8mm-ddrc";
+			reg = <0x3d400000 0x400000>;
+			clocks = <&clk IMX8MM_CLK_DRAM>;
+			operating-points-v2 = <&ddrc_opp_table>;
+		};
 	};
 };